1 Silicon Errata Summary
| Module | Feature | Issue Summary | Affected Revisions | |||
|---|---|---|---|---|---|---|
| PIC32CX5109BZ31048, WBZ351 | PIC32CX5109BZ31032, WBZ350 | PIC32CX5109BZ36048 | PIC32CX5109BZ36032 | |||
| A0 | B0 | |||||
| Supply Voltage and Power Mode | Device parts are not powering at 1.9V | Device parts are not powering at 1.9V | X | |||
| Supply Voltage and Power Mode | Power Management Support |
The PIC32CX-BZ3 Power Management Unit (PMU) supports only the MLDO mode only. The PIC32CX-BZ36 Power Management Unit (PMU) supports both MLDO and Buck mode. | X | |||
| Supply Voltage and Power Mode | System Does Not Enter Sleep Mode with Flash Power Down (NVMCON2.SLEEP = 0) Bit Disabled and System Clock Equal to or Less than the FRC Frequency | The system is
not entering the Sleep mode when the Flash power
down (NVMCON2.SLEEP = 0) bit is
disabled and the system is working at FRC
frequency. | X | |||
| Supply Voltage and Power Mode | GPIO Output Configuration in Deep Sleep and Extreme Deep Sleep |
In the Deep Sleep and Extreme Deep Sleep mode, GPIO must not be set to the output state of pin HIGH. Configuring the GPIO state to pin High during the Deep Sleep mode or Extreme Deep Sleep mode will causes leakage current and potential reliability issues on the silicon. This issue is only applicable when the CPU is in the Deep Sleep mode or Extreme Deep Sleep mode and when GPIO is configured as the output state pin HIGH. | X | |||
| Supply Voltage and Power Mode | GPIO Change Notification Interrupt Not Firing After Sleep |
Issue occurs when CNEN0x = 110 or 101. Device would not wake up on pin state change CNEN0x = 110, interrupt on change for a negative edge transition is enabled for PORTx[n] CNEN0x = 101, interrupt on change for a positive edge transition is enabled for PORTx[n] | X | X | ||
| Supply Voltage and Power Mode | POR Rearm Event | The POR event is not getting triggered even when the voltage is going below 1.45V. | X | X | ||
| Analog Comparator (AC) | AC_CMPx Output is Not Gated Either by COMPCTRLx.ENABLE or PMD1.ACMD | The Analog
Comparator output (AC_CMPx) will not be disabled
by setting either COMPCTRLx.ENABLE =
0 or PMD1.ACMD =
1. | X | |||
| Analog Comparator (AC) | Wrong VDD Scaler Reference for AC_CMP0 | AC_CMP0 uses a fixed VDD/2 reference, but the observed reference voltage is not equal to VDD/2. | X | |||
| Analog Comparator (AC) | Wrong VDD Scaler Reference with CMP0 and CMP1 Enabled Concurrently | An incorrect VDD scaler reference voltage is observed when AC_CMP0 and AC_CMP1 are enabled concurrently with VDD scaler as reference for both the comparators. Both comparators will see the same VDD scaler reference. | X | |||
| Analog-to-Digital Converter (ADC) | Improper Comparison Operation in Stand by Sleep Mode | A comparison in single shot mode will not be completed when entering in Standby sleep mode with RUNSTDBY=0. | X | X | ||
| Analog-to-Digital Converter (ADC) | Glitches in ADC Conversion Result | When the ADC Control clock is asynchronous with the System clock, the conversion result may have glitches if the CPU reads ADCBUFx while the new conversion result is being updated. | X | X | ||
| Analog-to-Digital Converter (ADC) | Wrong VDD33/2 for ADC Internal Input Channel AN11 | The ADC internal input channel, AN11, is connected with VDD33/2, but the observed input voltage is not equal to VDD/2. | X | X | ||
| Configurable Custom Logic (CCL) | Output Logic is Stuck when Enabling a LUT with Sequential Logic after the CCL is Enabled | When the LUT is disabled (LUTCTRL0.ENABLE=0 or LUTCTRL2.ENABLE=0) to clear the flip-flop/latch output, then enabled again, the sequential logic is kept under Reset. | X | X | ||
| Configurable Custom Logic (CCL) | PAC Error when Writing CCL.CTRL.SWRST Bit Description | Writing the Software Reset bit in the Control register (CTRL.SWRST) will trigger a PAC protection error. | X | X | ||
| Capacitive Voltage Divider (CVD) Controller | False CVD event | An invalid CVD event can be created while the FIFO counter is incrementing. | X | |||
| Direct Memory Access Controller (DMAC) | DMA Writeback Descriptor Corruption Issue |
Writeback descriptors could be corrupted on an active channel with ongoing transfers when another channel is being disabled or suspended | X | X | ||
| Direct Memory Access Controller (DMAC) | Fetch Error can Appear when Enable One Channel and Link Request on Another |
When at least one channel using linked descriptors is already active, a channel Fetch Error (FERR) may occur upon enabling a channel with no linked descriptor or the second descriptor (index 1) of the channel being enabled may be fetched by one of the already active channels using linked descriptors. These errors may happen when a channel is being enabled during the link request of another channel and if the channel number of the channel being enabled is lower than the channel already active. | X | X | ||
| External Interrupt Controller (EIC) | Asynchronous Edge Detection | When the asynchronous edge detection is enabled (without debouncer) and the system is in the Standby Sleep mode, only the first edge will generate an event. The edges following the first edge of the waveform do not generate events until the system wakes up. | X | X | ||
| External Interrupt Controller (EIC) | If NMI is Configured in Synchronous Edge Detection Mode, Spurious Interrupts may occur after a Software Reset | If the NMI is configured in synchronous edge detection mode (NMICTR.NMISENSE = 1, 2 or 3; NMICTRL.NMIASYNCH = 0), spurious NMI interrupts may occur after a software reset (CTRLA.SWRST = 1). | X | X | ||
| Event System (EVSYS) | Software Event | The BUSYCH flag never resets upon software events in synchronous/resynchronized path modes with event detection on falling edges. | X | X | ||
| Event System (EVSYS) | Spurious Overrun | The overrun interrupt flag may be incorrectly set upon software events in synchronous/resynchronized path modes with event detection on both rising and falling edges. | X | X | ||
| Event System (EVSYS) | Spurious Overrun | In the
Synchronous mode, spurious overrun interrupts can
happen when the generic clock for a channel is
always CHANNEL.ONDEMAND =
0. | X | |||
| Flash Controller Module | SYS Reset Not Getting Released when Asserted Post-Erase Retry | After the
Erase Retry operation (using NVMCON2.VREAD1 =
1), all the operations work as
expected until a SYS reset is asserted. After the
SYS reset is asserted post-Erase Retry, the reset
is stuck and is not being released. | X | X | ||
| Flash Controller Module | DMA in Sleep Mode | The Flash read/write by DMA is not working in Standby Sleep mode if the Flash power down is enabled. | X | X | ||
| Flash Controller Module | Risk of NMI False/Deep Power Down (DPD) | The NMI wakes while the CRU is entering Sleep mode and may trigger Flash DPD on early wake-up. | X | X | ||
| GPIO | GPIO Port Value unstable in Debug and Freeze Mode | Issue occurs when a signal changes on a GPIO pad and at the same time ICD freezes the GPIO peripheral. In this case reading the port register will result in unstable values for the pads that changed. | X | X | ||
| Peripheral Access Controller (PAC) | PAC Protection Error in FREQM | FREQM reads on the Control B register (FREQM.CTRLB) generate a PAC protection error. | X | X | ||
| Quad I/O Serial Peripheral Interface (QSPI) | QSPI Status Register Bits Not Updated when PB-Bridge-B (PB2_CLK) is Not Equal to System Clock (SYS_CLK) | If PB2_CLK is not equal to System Clock (sys_clk), the QSPI Status register bits are not updated. | X | X | ||
| RAM Error Correction Code (RAMECC) | ERRADDR Register May Read as ‘0’ When PB-Bridge-B (PB2_CLK) is Not Equal to System Clock (SYS_CLK) | If PB2_CLK is
not equal to the System clock (sys_clk), the
ERRADDR register read will not return the failing
address (caused by Single Bit Error/Dual Bit
Error); instead, it may return
‘0’. | X | X | ||
| RAM Error Correction Code (RAMECC) | 6 Bytes Not Retained at Address 0x20000006 Offset | When SRAM is configured for memory retention, 6 bytes of memory cannot be retained. | X | |||
| Real-Time Clock Calender (RTCC) | Tamper Input Filter |
Majority debouncing, as part of RTCC tamper detection, does not work when enabled by setting the Debouncer Majority Enable bit, CTRLB.DEBMAJ. | X | X | ||
| Real-Time Clock Calender (RTCC) | Write Corruption | An 8-bit or
16-bit write access for a 32-bit register or an
8-bit write access for a 16-bit register can fail
for the following registers:
| X | X | ||
| Real-Time Clock Calender (RTCC) | COUNTSYNC | When COUNTSYNC is enabled, the first COUNT value is not correctly synchronized and, thus, the value is incorrect. | X | X | ||
| Real-Time Clock Calender (RTCC) | Tamper Input Filter | Majority debouncing, as part of RTCC tamper detection, does not work when enabled by setting the Debouncer Majority Enable bit, CTRLB.DEBMAJ. | X | X | ||
| Real-Time Clock Calender (RTCC) | Tamper Detection |
When the RTCC is configured in ACTL mode with an external tamper pin (ALSI=0) and the RTCC CTRLA.ENABLE bit is not set, a tamper can be detected and a timestamp captured. The TAMID register and INTFLAG.TAMPER bit may be (not always) set. | X | X | ||
| Real-Time Clock Calender (RTCC) | Tamper Detection Timestamp |
If an external Reset occurs during a tamper detection, the TIMESTAMP register will not be updated when the next tamper detection is triggered. | X | X | ||
| Real-Time Clock Calender (RTCC) | Periodic Event Generation | When CTRLA.PRESCALER is set to OFF and either CTRLB.RTCCOUT is set or one of the TAMCTRL.DEBNCn bits is set, the RTCC prescaler behaves like CTRLA.PRESCALER = DIV1. The Periodic events and Periodic interrupts will be generated. | X | X | ||
| Real-Time Clock Calender (RTCC) | General Purpose Register |
General Purpose Registers n (GPn) are Reset on
tamper detection even if GPTRST =
| X | X | ||
| Real-Time Clock Calender (RTCC) | TIMESTAMP Lock by INFLAG.TAMPER | When DMA is enabled (CTRLB.DMAEN = 1), the INTFLAG.TAMPER bit is not reset by reading the TIMESTAMP register. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-USART: Collision Detection | In the USART
operating mode with Collision Detection enabled
(CTRLB.COLDEN = 1), the SERCOM
will not abort the current transfer as expected if
a collision is detected and if the SERCOM APB
(PBx_CLK) Clock is lower than the SERCOM Generic
Clock. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-USART: Debug Mode | In the USART
operating mode, if DBGCTRL.DBGSTOP =
1, data transmission is not
halted after entering the Debug mode. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-USART: Flow Control in 32-Bit Extension Mode | When the USART
is used in the 32-bit mode with hardware
handshaking (CTS/RTS), the TXC flag may be set
before transmission has completed. TXC may
incorrectly be set regardless of whether Data
Length Enable (LENGTH.LENEN) is set to
‘0’ or
‘1’. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-USART: Error Interrupts | The SERCOM USART does not wake from the Standby Sleep mode for ERROR interrupts FERR and PERR | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-USART: SERCOM USART in TX Mode Only | When the
SERCOM USART is configured as CTRLA.RUNSTDBY =
0 and the Receiver is disabled
(CTRLB.RXEN = 0), the clock
request to the SERCOM generic clock generator
feeding the SERCOM will stay asserted during the
Standby Sleep mode, leading to unexpected
overconsumption. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-I2C: I2C in Client Mode | In the I2C mode, the LENERR, SEXTOUT, LOWTOUT, COLL and BUSERR bits are not cleared when INTFLAG.AMATCH is cleared. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Client Mode with DMA | In the I2C Client Transmitter mode, at the reception of a NACK, if there is still data to be sent in the DMA buffer, the DMA will push data to the DATA register. Because a NACK was received, the transfer on the I 2C bus will not occur, causing the loss of this data. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-I2C: I2C Client in DATA32B Mode |
When SERCOM is configured as an I2C
client in the 32-bit Data mode (DATA32B =
If the CPU does not write a new data to the I2C client DATA register, the I2C client will pull the SDA line, which will result in stalling the bus permanently. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Repeated Start | When the Quick
command is enabled (CTRLB.QCEN =
1), software can issue a repeated
Start by writing either CTRLB.CMD or ADDR.ADDR bit
fields. If in these conditions the SCL Stretch
mode is CTRLA.SCLSM = 1, a bus
error will be generated. | X | |||
| Serial Communication Interface (SERCOM) | SERCOM-I2C: SCL/SDA Transition Time | SCL/SDA minimum transition time is not met in Fast-mode plus (1 MHz). | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-I2C Client: Error Interrupt INTFLAG.ERROR Repeated Start | When an unexpected STOP occurs on the I2C bus, the STATUS.BUSERR and INTFLAG.ERROR bits are set but may not wake the system from the Standby Sleep mode. An unexpected START will not produce this issue. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-I2C Client:I2C Client Auto Ack is Not Usable |
The I2C client AACKEN feature is not usable when doing a repeated start. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-I2C Client: I2C DRDY Raised when no Data is to be Fed |
The RXNACK status bit is invalid during the first I2CS_DRDY interruption handler. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-SPI: Data Preload | In the SPI
Client mode with Client Data Preload Enabled
(CTRLB.PLOADEN = 1), the client
transmitter may discard some data if the host
cannot keep the Client Select pin low until the
end of transmission. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-SPI: 32-Bit Extension Mode Additional Bytes | When the 32-bit extension mode is enabled and Data to be sent is not in multiples of 4 bytes (which means length counter needs to be enabled). In this case, additional byte(s) will be sent over the line. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-SPI: Client Data Preload | Preloading a
new SPI data (CTRLB.PLOADEN = 1)
before going into the Standby Sleep mode may lead
to extra power consumption. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-SPI: Hardware Client Select Control | When Hardware
Client Select Control is enabled (CTRLB.MSSEN =
1), the Client Select (SS) pin
goes high after each byte transfer even if new
data is ready to be sent. | X | X | ||
| Serial Communication Interface (SERCOM) | SERCOM-LIN: Two Stop Bits Mode is Not Supported in SERCOM USART LIN Host Mode | Two stop bits mode (CTRLB.SBMODE=0x1) is not supported in SERCOM USART LIN Host Mode (CTRLA.FORM=0x2) in the case where break, sync and identifier fields are automatically transmitted when DATA is written with the identifier (CTRLB.LINCMD=0x2). Only one stop bit mode is supported. | X | X | ||
| Timer/Counter for Control Applications (TCC) | LUPD in Descendent Mode |
When the TCC is used in the Down-counting mode, transfer of the PERBUF register value to the PER register is delayed by one counter cycle, and, therefore, the LUPD feature must not be used with the PER register. | X | X | ||
| Timer/Counter for Control Applications (TCC) | Corrupted Re-trigger Event Waveform Output | If a Re-trigger event (EVCTRL.EVACTn = 0x1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted. | X | X | ||
| Timer/Counter for Control Applications (TCC) | TCC Capture Mode with Synchronous Event | TCC input events does not support Synchronous or Resynchronized path. | X | X | ||
| Timer/Counter for Control Applications (TCC) | TCC in Dithering Mode with External Re-trigger Events | Using the TCC in the Dithering mode with external retrigger events can lead to an unexpected stretch of right-aligned pulses or shrink of left-aligned pulses. | X | X | ||
| Timer/Counter for Control Applications (TCC) | RAMP2 Feature in Down-Counting Mode | The
Timer/Counter counting-down mode (CTRLBCLR.DIR =
CTRLBSET.DIR = 1) is not
supported in RAMP2 operations (RAMP2, RAMP2A,
RAMP2C, RAMP2CS). | X | X | ||
| Timer/Counter for Control Applications (TCC) | In 2RAMP Mode with Hi-resolution Reference | In 2RAMP mode with Hi-resolution, multiple restarts can be observed when a fault occurred. | X | X | ||
| Timer/Counter (TC) | PERBUF/CCBUFx Register | When clearing the STATUS.PERBUFV/STATUS.CCBUFx flag, the SYNCBUSY flag is released before the PERBUF/CCBUFx register is restored to its appropriate value. | X | X | ||
| Timer/Counter (TC) | Re-trigger | If a Re-trigger event (EVCTRL.EVACTn = 0x1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted. | X | X | ||
| Watchdog Timer (WDT) | RUN Mode WDT Counter is Not Cleared Before Standby Sleep Instruction |
When the interval between clearing the watch dog timer and the sleep instruction is less than 1 WDT clock cycle, the Run mode watchdog counter is not cleared. While in the Standby Sleep mode, the Sleep mode watchdog counter is incrementing, and, at the end of the WDTPS, it generates an NMI which causes the CPU to wake up. After wake-up, the user will expect that because WDT is cleared just before going to sleep, they have an entire WDT period available to them before they have to clear WDT again. But because the Run mode counter was not cleared before going into sleep, the WDT Reset will occur earlier than expected. | X | X | ||
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