5 Device Operation
The AT25080B/AT25160B is controlled by a set of instructions sent from a host controller, commonly referred to as the SPI host. The SPI host communicates with the AT25080B/AT25160B via the SPI bus, which comprises four signal lines: Chip Select (CS), Serial Data Clock (SCK), Serial Data Input (SI) and Serial Data Output (SO).
The SPI protocol defines four modes of operation (Mode 0, 1, 2 and 3), with each mode differing in terms of SCK polarity and phase, which control the flow of data on the SPI bus. The AT25080B/AT25160B supports the two most common modes, SPI Modes 0 and 3. In SPI Modes 0 and 3, data are always latched in on the rising edge of SCK and output on the falling edge of SCK. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the Inactive state (when the SPI host is in Standby mode and not transferring any data). SPI Mode 0 is defined as having SCK low while CS is not asserted (at VCC), whereas SPI Mode 3 has SCK high in the Inactive state. The SCK Idle state must match when CS is deasserted, both before and after the communication sequence, in SPI Modes 0 and 3. The figures in this document depict Mode 0 with a solid line on SCK while CS is inactive and Mode 3 with a dotted line.