1.4.1.4 User Control of Output Clock Port Pattern on IOD Generic Transmit Interface

Libero SoC v2021.2 adds an option to enable user control of the output clock port (HS_CLK) pattern on the PF_IOD_GENERIC_TX interface.

For more information, see the PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide.