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Release Notes Libero® SoC v2021.2
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Libero SoC Software Release Notes
1.3
Software Features and Enhancements
Libero® SoC v2021.2
Introduction
Related Release Notes
1
Libero SoC Software Release Notes
1.1
Customer Notification (CN) Support
1.2
New Device Support
1.3
Software Features and Enhancements
1.3.1
Smart High-Level Synthesis (SmartHLS) general release v2021.2
1.3.2
SmartDesign Enhancements
1.3.3
Bitstream Digest
1.3.4
Out-of-Context Derive Constraints Utility for Custom Flows
1.3.5
Timing Constraint Enhancements: Multi-cycle Start and End Options
1.3.6
Ability to Create and Select Synthesis and Identify Implementations
1.3.7
SynplifyPro and Identify
1.3.8
Initiator/Target Nomenclature
1.3.9
Standalone Synthesis Flow
1.3.10
Discontinuation of ModelSim ME
1.4
New Silicon Features and Enhancements
2
Migrating Designs to Libero SoC 2021.2
3
Resolved Issues
4
Known Issues and Limitations
5
System Requirements
6
Download Libero SoC Software
7
Documents Updated in This Release
8
Revision History
Microchip FPGA Support
The Microchip Website
Product Change Notification Service
Customer Support
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System
Worldwide Sales and Service
1.3 Software Features and Enhancements
