4 Example 2: SPI Communication Controlled by Interrupts

In master mode, interrupt controlled communication makes mainly sense if the SCK clock is generated by dividing the system clock by a large division factor (like 64 or 128). In this case the processor can perform other processes instead of just waiting to send/receive the next byte. In slave mode, where the part does not know when a communication starts, an interrupt controlled implementation can ensure that the part will react in time so that write collision errors will be avoided.