2.5.1 Frequency Change Monitor

The frequency change monitor provides the following scenarios:

• The frequency change monitor takes the recovered clock as input and monitors the frequency change with respect to a stable clock.
• The logic checks the frequency of the clock at fixed intervals and determines the stability of the clock. If the deviation in the frequency exceeds the predetermined limits, a link loss signal is asserted, and the japll_controller is informed of a break link condition.