2.5.2 JAPLL Controller
(Ask a Question)The following figure shows the JAPLL controller subsystem interface.
japll_controller implements a DRI initiator interface to interact with the JAPLL through a PF_DRI core.
Fabric logic and the PF_DRI core operates on the same frequency of 50 MHz. Enabling and disabling of syncE is done based on the requests received from the ESMC IP. After power-up, JAPLL will be locked to the external auxiliary clock. When the en_synce command is received from the ESMC IP, JAPLL controller executes a sequence of steps for the JAPLL to switch its input to the cdr recovered clock. JAPLL generates the INT and FRAC values which are derived based on the cdr recovered clock. TX clock synchronizes with the recovered clock to show that synchronous Ethernet is enabled. For more information, see Hitless Clock Switching: Enable SyncE.
When the dis_synce command is received from ESMC IP, JAPLL input is switched back to the local auxiliary clock. JAPLL generates the INT and FRAC values based on the local auxiliary clock. The TX clock synchronizes with the local auxiliary clock to prove that synchronous Ethernet is disabled. For more information, see Hitless Clock Switching: Disable SyncE.
Japll_apb3_master performs the following register write operations.
| Function | Register | Description |
|---|---|---|
| Write | EXT_PLL_JA_8 | Enabling/disabling JA_HOLD and PRESET_EN |
| Write | EXT_PLL_JA_8 | Load FRAC PRESET value |
| Write | EXTPLL_JA_9 | Load INT_PRESET value |
| Write | DES_RSTPD | For RX power-down and power-up |
| Read | EXTPLL_JA_10 | Read JAPLL Flock and Plock values |
| Read | EXTPLL_JA_9 | Read INT_PD_OUT value |
| Read | EXTPLL_JA_10 | Read FRAC_PD_OUT value |
JAPLL Controller handles two different scenarios in this reference design. The following figure shows the reference design.
JAPLL Controller handles the following functions:
- Load the JAPLL with the default INT and FRAC preset values
- Hitless Clock Switching: Enable SyncE and Disable SyncE
- Read the JAPLL phase detector output every 11.4 ms
- Implementing the averaging algorithm
- Load the JAPLL with the computed averaged INT preset value
- Handling the break-link and make-link conditions
These scenarios are described in the following sections.