There are three clock domains in the reference designs; RX_CLK (161.13 MHz), TX_CLK (161.13 MHz), and CLK_156pt25 (156.25 MHz). The following figure shows the clocking structure.Figure 2-7. Clocking Structure
The following table lists the clock descriptions.
Table 2-3. Clocks
Clock Name
Frequency
Instance Name
clk_156pt25 MHz
156.25
esmc_tx_subsystem_0
esmc_rx_subsystem_0
clk_78pt125 MHz
78.125
esmc_tx_subsystem_0
esmc_rx_subsystem_0
UART_IF_0
TX_CLK_R
161.13
CORE10GMAC0_0
RX_CLK_R
161.13
CORE10GMAC0_0
Frequency_change_monitor_0
clk_156pt25 MHz
156.25
CORE10GMAC0_0
clk_50 MHz
50
CORE10GMAC_SUBSYSTEM
Japll_controller_0
PF_DRI_0
COREABC0_0
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