2.3.1 ESMC TX Subsystem

ESMC TX subsystem consists of the following modules:

  • pdu_generator: This module handles the following features:
    • pdu_generate_request_servicing: This module services the request received from the pdu_checker and also generates an acknowledgment signal to indicate the successful transmission of PDU.
    • pdu_packet_framer: This module frames 58-byte packet based on a different type of PDU request received. Currently, the framer accepts a request to generate 10 different PDU's.
    • pdu_counter_logic: Counter logic to keep a log of how many PDU's have been sent out. Current logic keeps track of all the different types of PDU's sent.
    • pdu_sent_max_threshold: Logic to limit the number of PDU's that can be sent using a 1 second timer.
  • fifo_mgmt: FIFO management module is used to efficiently manage the clock domain crossing between a PDU generator (slow clock domain) and Core10GMAC (fast clock domain). The module also consists of a controller that manages the writes and reads for a group of 10 FIFO's.

    • FIFO controller reads from FIFO when i_sys_mac_tx_fifo_af signal is "0".

    • The writes to the FIFO's are performed by pdu_generator when a "PDU send" request is generated from the Rx subsystem.

The following figure shows the PDU generator finite state machine.

Figure 2-3. PDU Generator Finite State Machine

PDU generator finite state machine traverses through the following states when any one of the send PDU requests are received:

  • IDLE: Check for any of the PDU send requests for "1" and then traverse to STATE_DWORD1.
  • STATE_DWORD1 to STATE_DWORD8: The framer accesses the predefined data word from the defined file based on the request sent from pdu_checker and also traverses to the next state.
  • WAIT_STATE: Logic checks for any of the PDU send requests to be "1" and then traverse to the IDLE state.