2.3.2 ESMC RX Subsystem

ESMC RX subsystem consists of the following modules:

  • pdu_parser: It implements a FIFO management system to detect and store the ESMC PDU by checking the Destination Address (48'h0180_C200_0002).
    • Header decoder
    • Storing pdu
  • pdu_checker: This module handles the following features:
    • pdu_info_extraction: A finite state machine decodes and stores the data fields from the received PDU.
    • ql_priority_selection_algo: Logic to compares the local QL value with the decoded QL value and selects the QL value which has higher priority (better clock quality).
    • pdu_generation_request: When ql_enabled is "0", a DNU info pdu send request is sent to the pdu_generator, whereas when ql_enabled is "1", pdu_checker module sends a pdu generation request to pdu_generator based on the result of QL selection logic.
    • Port availability information

The following figure shows the PDU checker finite state machine.

Figure 2-4. PDU Checker Finite State Machine

PDU checker finite state machine traverses through the following states when any of the send PDU requests are received:

  • The Enabling Jitter Cleaner mode has the following scenarios:

    • After reset is de-asserted enable_japll signal is "1", when pdu_data_ready signal is "1", pdu_checker will deassert the JAPLL by setting enable_japll to "0".
    • This sequence is performed only once when ql_enable is "1" to show the actual working of the jitter cleaner PLL.
    • Enable_japll will remain "0", until there is any change in the input QL value.
    • If the QL selection logic detects a change in the input QL value, enable_japll becomes "1" for the transmitter to lock to the new clock reference which has a better clock quality than the local reference clock.