| Document |
- Data sheet status changed to “Completed”: final
limits added to the Electrical Characteristics,
Typical Characteristics expanded, and package top
markings added
- Number of available AC input pins corrected for
ATtiny1624, ATtiny1626 in Table 2. Peripheral
Overview
- Editorial updates throughout the document
|
| CPU |
- RAMPZ description updated
- EICALL not present/required in the tiny
2-family
|
| Fuses | Reserved bits are written to ‘1’, so the
factory default values are:- OSCCFG:
0x7E - SYSCFG0:
0xF6 - SYSCFG1:
0xFF
|
| NVMCTRL |
- Table 10-1. Setting Up Flash Sections: When
BOOTEND =
0, the value of APPEND
is ignored, and the entire Flash is BOOT
section. - Register CTRLB has Configuration Change
Protection
|
| RSTCTRL | Figures and timing diagrams improved:- Block Diagram: improved
- MCU Start-Up
- Brown-Out Detector Reset
- Software Reset
|
| CPUINT | Description of the IVSEL bit in the CTRLA register
improved: When the entire Flash is configured as BOOT
section, the IVSEL bit in the CTRLA register is
ignored. |
| PORT | Slew rate limitation functionality added: Slew Rate Limit
Enable (SLR) bit in the Port Control (PORTCTRL)
register. |
| TCA |
- Split mode interrupts added to Interrupt Vector
Table
- Timing diagram for Split mode added
- Block diagram: The path from CNT register to
CMPnBUF register removed
- In TCA Frequency mode, the timer frequency is
controlled by CMP0, not CMPn
|
| TCB |
- 32-bit input capture is working for all input
capture modes
- In Single-Shot mode, when the EDGE bit in the
EVCTRL register is ‘
1’, both
positive and negative edges will start the
counter
|
| RTC | It is no longer required to check the Synchronization
Busy bits in the STATUS and PITSTATUS registers after
startup |
| USART |
- Description of the TX buffer added
- Description of the IREI bit in the EVCTRL
register corrected
|
| TWI |
- FLUSH and BUSSTATE description updated
- CTRLA.SDASETUP is used in client mode to select
the clock hold time to ensure minimum setup
time
|
| ADC |
- Description of COMMAND.START bit field
improved
- PGA initialization time is 20 µs
- Group configuration names aligned with header
files for PGACTRL.PGABIASSEL and
MUXNEG.MUXNEG
|
| UPDI | Value of STATUSA.UPDIREV corrected to
‘0100’ |
| Electrical Characteristics |
|
| Typical Characteristics | Plots added |
