43.6.1 Channel Context

Channel context refers to the unique set of control, status and data register configurations that define the operation of the ADC for a specific type of conversion. For example, if the ADC is configured for Burst Average mode, that configuration can be saved as a channel context. Up to four channel contexts can be configured for sequencing. Context information is stored in duplicated registers located in device memory and can only be accessed through the A/D Context Selection (ADCTX) Register or via Direct Memory Access (DMA).

Important: The ADCLK and ADACT registers are not included as part of a channel context.

The conversion clock rate selected by ADCLK and the auto-conversion trigger source selected by ADACT are used for all contexts. For example, if Context 1 enables the Timer1 overflow as the auto-conversion trigger source, the Timer1 overflow trigger will be used for all other contexts as well. If user software configures the auto-conversion trigger to use the Timer0 overflow as the trigger source for Context 2, Context 1 will be reconfigured in hardware to also use the Timer0 overflow as the trigger source.

The table below highlights the registers that are part of a context.

Table 43-4. ADC Context Registers
Register	Bit Pos.	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
ADCON0⁽¹⁾	7:0	ON	CONT	CSEN	CS		FM		GO
ADCON1	7:0	PPOL	IPEN	GPOL					DSEN
ADCON2	7:0	PSIS	CRS[2:0]			ACLR	MD[2:0]
ADCON3	7:0		CALC[2:0]			SOI	TMD[2:0]
ADSTAT	7:0	AOV	UTHR	LTHR	MATH		STAT[2:0]
ADREF	7:0				NREF			PREF[1:0]
ADPCH	7:0			PCH[5:0]
ADPRE	7:0	PRE[7:0]
ADPRE	15:8					PRE[12:8]
ADACQ	7:0	ADACQ[7:0]
ADACQ	15:8					ADACQ[12:8]
ADCAP	7:0				CAP[4:0]
ADRPT	7:0	RPT[7:0]
ADCNT	7:0	CNT[7:0]
ADFLTR	7:0	FLTR[7:0]
ADFLTR	15:8	FLTR[15:8]
ADRES	7:0	RES[7:0]
ADRES	15:8	RES[15:8]
ADPREV	7:0	PREV[7:0]
ADPREV	15:8	PREV[15:8]
ADACC	7:0	ACC[7:0]
	15:8	ACC[15:8]
	23:16							ACC[17:16]
ADSTPT	7:0	STPT[7:0]
ADSTPT	15:8	STPT[15:8]
ADERR	7:0	ERR[7:0]
ADERR	15:8	ERR[15:8]
ADLTH	7:0	LTH[7:0]
ADLTH	15:8	LTH[15:8]
ADUTH	7:0	UTH[7:0]
ADUTH	15:8	UTH[15:8]

Note:

The ADCON0 register is not included as part of a channel context with the exception of bit 6 (CONT).

The A/D Context Selection (ADCTX) register selects the context number that will be given read/write access. The A/D Context Display Select (CTXSW) bit is used to determine the read/write status of the A/D Channel Context Selection (CTX) bits, which are used to determine the channel context number.

When CTXSW is set (CTXSW = 1), the CTX bits display the context number the sequencer is currently scanning or the context number that was active when the sequencer stopped scanning due to a context threshold interrupt.

Important: When CTXSW is set, the CTX bits are read-only and may only be read while context sequencing is enabled (CSEN = 1).

When CTXSW is clear (CTXSW = 0), the CTX bits display the context number as selected by user software. Any context can be selected by writing the CTX bits with the desired context number.