42.5.5 OPAxHWC
| Name: | OPAxHWC |
| Address: | 0xA7 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| OREN | HWCH[2:0] | ORPOL | HWCL[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – OREN Override Enable
| Value | Description |
|---|---|
| 1 | Hardware Override Control is enabled. OPA mode of operation is configured using the HWCH / HWCL bits. |
| 0 | Hardware Override Control is disabled. OPA mode of operation must be configured in software. |
Bits 6:4 – HWCH[2:0] Hardware Control Configuration High
| Value | Description |
|---|---|
111 |
Rail Drive to VDD |
110 |
Reserved |
101 |
Reserved |
100 |
Basic OPA configuration with unity gain feedback |
011 |
Reserved |
010 |
Reserved |
001 |
Reserved |
000 |
Basic OPA configuration with user-defined feedback |
Bit 3 – ORPOL Override Source Polarity
| Value | Description |
|---|---|
| 1 | Hardware Control Input is Inverted (Active-Low) |
| 0 | Hardware Control Input is not Inverted (Active-High) |
Bits 2:0 – HWCL[2:0] Hardware Control Configuration Low
| Value | Description |
|---|---|
111 |
Rail Drive to VSS |
110 |
Reserved |
101 |
Reserved |
100 |
Basic OPA configuration with unity gain feedback |
011 |
Reserved |
010 |
Reserved |
001 |
Reserved |
000 |
Basic OPA configuration with user-defined feedback |