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14/20-Pin, Low-Power, High-Performance Microcontroller with XLP Technology
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PIC18F06Q41
PIC18F16Q41
Introduction
PIC18-Q41
Family Types
Features
Memory
Operating Characteristics
Power-Saving Functionality
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
PIC18-Q41 Block Diagram
1
Packages
2
Pin Diagrams
3
Pin Allocation Tables
4
Guidelines for Getting Started with
PIC18-Q41
Microcontrollers
4.1
Basic Connection Requirements
4.2
Power Supply Pins
4.3
Master Clear (
MCLR
) Pin
4.4
In-Circuit Serial Programming™ (ICSP™) Pins
4.5
External Oscillator Pins
4.6
Unused I/Os
5
Register and Bit Naming Conventions
5.1
Register Names
5.2
Bit Names
5.3
Register and Bit Naming Exceptions
6
Register Legend
7
PIC18 CPU
7.1
System Arbitration
7.2
Memory Access Scheme
7.3
8x8 Hardware Multiplier
7.4
PIC18 Instruction Cycle
7.5
STATUS Register
7.6
Call Shadow Register
7.7
Register Definitions: System Arbiter
7.8
Register Summary - System Arbiter Control
8
Device Configuration
8.1
Configuration Settings
8.2
Code Protection
8.3
User ID
8.4
Device ID and Revision ID
8.5
Register Definitions: Configuration Settings
8.6
Register Summary - Configuration Settings
8.7
Register Definitions: Device ID and Revision ID
8.8
Register Summary - DEVID/REVID
9
Memory Organization
9.1
Program Memory Organization
9.2
Device Information Area
9.3
Device Configuration Information
9.4
Data Memory Organization
9.5
Data Addressing Modes
9.6
Data Memory and the Extended Instruction Set
9.7
Register Definitions: Memory Organization
9.8
Register Summary - Memory Organization
10
NVM - Nonvolatile Memory Module
10.1
Operations
10.2
Unlock Sequence
10.3
Program Flash Memory (PFM)
10.4
Data Flash Memory (DFM)
10.5
Register Definitions: NVM
10.6
Register Summary - NVM
11
VIC - Vectored Interrupt Controller Module
11.1
Overview
11.2
Interrupt Control and Status Registers
11.3
Interrupt Vector Table
11.4
Interrupt Priority
11.5
Interrupt Operation
11.6
Context Saving
11.7
Returning from Interrupt Service Routine (ISR)
11.8
Interrupt Latency
11.9
Interrupt Setup Procedure
11.10
External Interrupt Pins
11.11
Wake-Up from Sleep
11.12
Interrupt Compatibility
11.13
Register Definitions: Interrupt Control
11.14
Register Summary - Interrupts
12
OSC - Oscillator Module (With Fail-Safe Clock Monitor)
12.1
Clock Source Types
12.2
Clock Switching
12.3
Fail-Safe Clock Monitor (FSCM)
12.4
Active Clock Tuning (ACT)
12.5
Register Definitions: Oscillator Module
12.6
Register Summary - Oscillator Module
13
CRC - Cyclic Redundancy Check Module with Memory Scanner
13.1
Module Overview
13.2
Polynomial Implementation
13.3
Data Sources
13.4
CRC Check Value
13.5
CRC Interrupt
13.6
Configuring the CRC Module
13.7
Scanner Module Overview
13.8
Scanning Modes
13.9
Configuring the Scanner
13.10
Scanner Interrupt
13.11
Peripheral Module Disable
13.12
Register Definitions: CRC and Scanner Control
13.13
Register Summary - CRC
14
Resets
14.1
Power-on Reset (POR)
14.2
Brown-out Reset (BOR)
14.3
Low-Power Brown-out Reset (LPBOR)
14.4
MCLR
Reset
14.5
Windowed Watchdog Timer (WWDT) Reset
14.6
RESET Instruction
14.7
Stack Overflow/Underflow Reset
14.8
Programming Mode Exit
14.9
Power-up Timer (PWRT)
14.10
Start-Up Sequence
14.11
Determining the Cause of a Reset
14.12
Power Control (PCON0/PCON1) Registers
14.13
Register Definitions: Power Control
14.14
Register Summary - BOR Control and Power Control
15
WWDT - Windowed Watchdog Timer
15.1
Independent Clock Source
15.2
WWDT Operating Modes
15.3
Time-Out Period
15.4
Watchdog Window
15.5
Clearing the Watchdog Timer
15.6
Operation During Sleep
15.7
Register Definitions: Windowed Watchdog Timer Control
15.8
Register Summary - WDT Control
16
DMA - Direct Memory Access
16.1
DMA Registers
16.2
DMA Organization
16.3
DMA Interface
16.4
Disable DMA Message Transfer Upon Completion
16.5
Types of Hardware Triggers
16.6
Types of Data Transfers
16.7
DMA Interrupts
16.8
DMA Setup and Operation
16.9
Reset
16.10
Power-Saving Mode Operation
16.11
Example Setup Code
16.12
Register Overlay
16.13
Register Definitions: DMA
16.14
Register Summary - DMA
17
Power-Saving Modes
17.1
Doze Mode
17.2
Sleep Mode
17.3
Idle Mode
17.4
Peripheral Operation in Power-Saving Modes
17.5
Register Definitions: Power-Savings Control
17.6
Register Summary - Power-Savings Control
18
PMD - Peripheral Module Disable
18.1
Overview
18.2
Disabling a Module
18.3
Enabling a Module
18.4
Register Definitions: Peripheral Module Disable
18.5
Register Summary - PMD
19
I/O Ports
19.1
Overview
19.2
PORTx - Data Register
19.3
LATx - Output Latch
19.4
TRISx - Direction Control
19.5
ANSELx - Analog Control
19.6
WPUx - Weak Pull-Up Control
19.7
INLVLx - Input Threshold Control
19.8
SLRCONx - Slew Rate Control
19.9
ODCONx - Open-Drain Control
19.10
Edge Selectable Interrupt-on-Change
19.11
I
2
C Pad Control
19.12
I/O Priorities
19.13
MCLR
/V
PP
/RA3
Pin
19.14
Register Definitions: Port Control
19.15
Register Summary - I/O Ports
20
IOC - Interrupt-on-Change
20.1
Overview
20.2
Enabling the Module
20.3
Individual Pin Configuration
20.4
Interrupt Flags
20.5
Clearing Interrupt Flags
20.6
Operation in Sleep
20.7
Register Definitions: Interrupt-on-Change Control
20.8
Register Summary - Interrupt-on-Change Control
21
PPS - Peripheral Pin Select Module
21.1
Overview
21.2
PPS Inputs
21.3
PPS Outputs
21.4
Bidirectional Pins
21.5
PPS Lock
21.6
Operation During Sleep
21.7
Effects of a Reset
21.8
Register Definitions: Peripheral Pin Select (PPS)
21.9
Register Summary - Peripheral Pin Select Module
22
CLC - Configurable Logic Cell
22.1
CLC Setup
22.2
CLC Interrupts
22.3
Effects of a Reset
22.4
Output Mirror Copies
22.5
Operation During Sleep
22.6
CLC Setup Steps
22.7
Register Overlay
22.8
Register Definitions: Configurable Logic Cell
22.9
Register Summary - CLC Control
23
CLKREF - Reference Clock Output Module
23.1
Clock Source
23.2
Programmable Clock Divider
23.3
Selectable Duty Cycle
23.4
Operation in Sleep Mode
23.5
Register Definitions: Reference Clock
23.6
Register Summary - Reference CLK
24
TMR0 - Timer0 Module
24.1
Timer0 Operation
24.2
Clock Selection
24.3
Timer0 Output and Interrupt
24.4
Operation During Sleep
24.5
Register Definitions: Timer0 Control
24.6
Register Summary - Timer0
25
TMR1 - Timer1 Module with Gate Control
25.1
Timer1 Operation
25.2
Clock Source Selection
25.3
Timer1 Prescaler
25.4
Secondary Oscillator
25.5
Timer1 Operation in Asynchronous Counter Mode
25.6
Timer1 16-Bit Read/Write Mode
25.7
Timer1 Gate
25.8
Timer1 Interrupt
25.9
Timer1 Operation During Sleep
25.10
CCP Capture/Compare Time Base
25.11
CCP Special Event Trigger
25.12
Peripheral Module Disable
25.13
Register Definitions: Timer1 Control
25.14
Register Summary - Timer1
26
TMR2 - Timer2 Module
26.1
Timer2 Operation
26.2
Timer2 Output
26.3
External Reset Sources
26.4
Timer2 Interrupt
26.5
PSYNC Bit
26.6
CSYNC Bit
26.7
Operating Modes
26.8
Operation Examples
26.9
Timer2 Operation During Sleep
26.10
Register Definitions: Timer2 Control
26.11
Register Summary - Timer2
27
SMT - Signal Measurement Timer
27.1
SMT Operation
27.2
Register Definitions: SMT Control
27.3
Register Summary - SMT Control
28
CCP - Capture/Compare/PWM Module
28.1
CCP Module Configuration
28.2
Capture Mode
28.3
Compare Mode
28.4
PWM Overview
28.5
Register Definitions: CCP Control
28.6
Register Summary - CCP Control
29
Capture, Compare, and PWM Timers Selection
29.1
Register Definitions: Capture, Compare, and PWM Timers Selection
29.2
Register Summary - Capture, Compare, and PWM Timers Selection
30
PWM - Pulse-Width Modulator with Compare
30.1
Output Slices
30.2
Period Timer
30.3
Clock Sources
30.4
External Period Resets
30.5
Buffered Period and Parameter Registers
30.6
Synchronizing Multiple PWMs
30.7
Interrupts
30.8
Operation During Sleep
30.9
Register Definitions: PWM Control
30.10
Register Summary - PWM
31
CWG - Complementary Waveform Generator Module
31.1
Fundamental Operation
31.2
Operating Modes
31.3
Clock Source
31.4
Selectable Input Sources
31.5
Output Control
31.6
Dead-Band Control
31.7
Rising Edge and Reverse Dead Band
31.8
Falling Edge and Forward Dead Band
31.9
Dead-Band Jitter
31.10
Auto-Shutdown
31.11
Auto-Shutdown Restart
31.12
Operation During Sleep
31.13
Configuring the CWG
31.14
Register Definitions: CWG Control
31.15
Register Summary - CWG
32
NCO - Numerically Controlled Oscillator Module
32.1
NCO Operation
32.2
Fixed Duty Cycle Mode
32.3
Pulse Frequency Mode
32.4
Output Polarity Control
32.5
Interrupts
32.6
Effects of a Reset
32.7
Operation in Sleep
32.8
Register Definitions: NCO
32.9
Register Summary - NCO
33
DSM - Data Signal Modulator Module
33.1
DSM Operation
33.2
Carrier Synchronization
33.3
Carrier Source Polarity Select
33.4
Programmable Modulator Data
33.5
Modulated Output Polarity
33.6
Operation in Sleep Mode
33.7
Effects of a Reset
33.8
Peripheral Module Disable
33.9
Register Definitions: Modulation Control
33.10
Register Summary - DSM
34
UART - Universal Asynchronous Receiver Transmitter with Protocol Support
34.1
UART I/O Pin Configuration
34.2
UART Asynchronous Modes
34.3
DMX Mode (Full-Featured UARTs Only)
34.4
LIN Modes (Full-Featured UARTs Only)
34.5
DALI Mode (Full-Featured UARTs Only)
34.6
General Purpose Manchester (Full-Featured UARTs Only)
34.7
Polarity
34.8
Stop Bits
34.9
Operation After FIFO Overflow
34.10
Receive and Transmit Buffers
34.11
Flow Control
34.12
Checksum (Full-Featured UARTs Only)
34.13
Collision Detection (Full-Featured UARTs Only)
34.14
RX/TX Activity Time-Out
34.15
Clock Accuracy with Asynchronous Operation
34.16
UART Baud Rate Generator
34.17
Transmitting a Break
34.18
Receiving a Break
34.19
UART Operation During Sleep
34.20
Register Definitions: UART
34.21
Register Summary - UART
35
SPI - Serial Peripheral Interface Module
35.1
SPI Controls
35.2
SPI Operation
35.3
Host Mode
35.4
Client Mode
35.5
SPI Operation in Sleep Mode
35.6
SPI Interrupts
35.7
Register Definitions: Serial Peripheral Interface
35.8
Register Summary - SPI Control
36
I
2
C - Inter-Integrated Circuit Module
36.1
I
2
C Features
36.2
I
2
C Terminology
36.3
I
2
C Module Overview
36.4
I
2
C Operation
36.5
Register Definitions: I
2
C Control
36.6
Register Summary - I
2
C
37
HLVD - High/Low-Voltage Detect
37.1
Operation
37.2
Setup
37.3
Current Consumption
37.4
HLVD Start-Up Time
37.5
Applications
37.6
Operation During Sleep
37.7
Operation During Idle and Doze Modes
37.8
Effects of a Reset
37.9
Register Definitions: HLVD Control
37.10
Register Summary - HLVD
38
FVR - Fixed Voltage Reference
38.1
Independent Gain Amplifiers
38.2
FVR Stabilization Period
38.3
Register Definitions: FVR
38.4
Register Summary - FVR
39
Temperature Indicator Module
39.1
Module Operation
39.2
Temperature Calculation
39.3
ADC Acquisition Time
39.4
Register Definitions: Temperature Indicator
39.5
Register Summary - Temperature Indicator
40
ADCC - Analog-to-Digital Converter with Computation Module
40.1
ADC Configuration
40.2
ADC Operation
40.3
ADC Acquisition Requirements
40.4
ADC Charge Pump
40.5
Computation Operation
40.6
Capacitive Voltage Divider (CVD) Features
40.7
Register Definitions: ADC Control
40.8
Register Summary - ADC
41
DAC - Digital-to-Analog Converter Module
41.1
Output Voltage Selection
41.2
Ratiometric Output Level
41.3
Operation During Sleep
41.4
Effects of a Reset
41.5
Register Definitions: DAC Control
41.6
Register Summary - DAC
42
OPA - Operational Amplifier
42.1
OPA Module Control
42.2
Hardware Override Control
42.3
Input Offset Voltage
42.4
OPA Operation with ADC
42.5
Register Definitions: Operational Amplifier
42.6
Register Summary - Operational Amplifier
43
CMP - Comparator Module
43.1
Comparator Overview
43.2
Comparator Control
43.3
Comparator Output Synchronization
43.4
Comparator Hysteresis
43.5
Comparator Interrupt
43.6
Comparator Positive Input Selection
43.7
Comparator Negative Input Selection
43.8
Comparator Response Time
43.9
Analog Input Connection Considerations
43.10
Operation in Sleep Mode
43.11
ADC Auto-Trigger Source
43.12
Register Definitions: Comparator Control
43.13
Register Summary - Comparator
44
ZCD - Zero-Cross Detection Module
44.1
External Resistor Selection
44.2
ZCD Logic Output
44.3
ZCD Logic Polarity
44.4
ZCD Interrupts
44.5
Correction for Z
CPINV
Offset
44.6
Handling V
PEAK
Variations
44.7
Operation During Sleep
44.8
Effects of a Reset
44.9
Disabling the ZCD Module
44.10
Register Definitions: ZCD Control
44.11
Register Summary - ZCD
45
Instruction Set Summary
45.1
Standard Instruction Set
45.2
Extended Instruction Set
46
ICSP™ - In-Circuit Serial Programming™
46.1
High-Voltage Programming Entry Mode
46.2
Low-Voltage Programming Entry Mode
46.3
Common Programming Interfaces
47
Register Summary
48
Electrical Specifications
48.1
Absolute Maximum Ratings
(†)
48.2
Standard Operating Conditions
48.3
DC Characteristics
48.4
AC Characteristics
49
DC and AC Characteristics Graphs and Tables
49.1
Analog-to-Digital Converter (12-bit) Graphs
49.2
Brown-Out Reset Graphs
49.3
Digital-to-Analog Converter Graphs
49.4
Fixed Voltage Reference Graphs
49.5
HFINTOSC Graphs
49.6
HFINTOSC Wake From Sleep Graphs
49.7
High/Low-Voltage Detect Graphs
49.8
I/O Graphs
49.9
I
DD
Graphs
49.10
I
PD
Graphs
49.11
LFINTOSC Graphs
49.12
LFINTOSC Wake From Sleep Graphs
49.13
Low-Power Brown-Out Reset Graphs
49.14
MFINTOSC Graphs
49.15
Operational Amplifier Graphs
49.16
Power-On Reset Graphs
49.17
Weak Pull-Up Graphs
50
Packaging Information
50.1
Package Details
51
Appendix A: Revision History
Microchip Information
The Microchip Website
Product Change Notification Service
Customer Support
Product Identification System
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
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