8.5.4 CONFIG4

Configuration Byte 4
Name: CONFIG4
Address: 0x300003

Bit 76543210 
 XINST LVPSTVRENPPS1WAYZCDBORV[1:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 1111111 

Bit 7 – XINST Extended Instruction Set Enable

ValueDescription
1 Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode)
0 Extended Instruction Set and Indexed Addressing mode enabled

Bit 5 – LVP Low-Voltage Programming Enable

The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally eliminating LVP mode from the Configuration state.
ValueDescription
1 Low-Voltage Programming enabled. MCLR/VPP pin function is MCLR. The MCLRE Configuration bit is ignored.
0 HV on MCLR/VPP must be used for programming

Bit 4 – STVREN Stack Overflow/Underflow Reset Enable

ValueDescription
1 Stack Overflow or Underflow will cause a Reset
0 Stack Overflow or Underflow will not cause a Reset

Bit 3 – PPS1WAY PPSLOCKED One-Way Set Enable

ValueDescription
1 The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented
0 The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required)

Bit 2 – ZCD ZCD Disable

ValueDescription
1 ZCD disabled, ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0 ZCD always enabled, PMDx[ZCDMD] bit is ignored

Bits 1:0 – BORV[1:0]  Brown-out Reset Voltage Selection

ValueDescription
11 Brown-out Reset Voltage (VBOR) set to 1.90V
10 Brown-out Reset Voltage (VBOR) set to 2.45V
01 Brown-out Reset Voltage (VBOR) set to 2.7V
00 Brown-out Reset Voltage (VBOR) set to 2.85V