Right/Left/Center/Variable-Aligned modes of operation
Multiple clock and Reset
signal selections
Three 16-Bit Timers (TMR0/1/3)
Two 8-Bit Timers (TMR2/4) with
Hardware Limit Timer (HLT)
Four Configurable Logic Cell
(CLC):
Integrated combinational and
sequential logic
One Complimentary Waveform Generator
(CWG):
Rising and falling edge
dead-band control
Full-bridge, half-bridge,
1-channel drive
Multiple signal sources
Programmable dead band
Fault-shutdown input
One Capture/Compare/PWM (CCP)
module:
16-bit resolution for
Capture/Compare modes
10-bit resolution for PWM
mode
One Numerically Controlled Oscillator
(NCO):
Generates true linear
frequency control and increased frequency resolution
Input clock up to 64 MHz
Signal Measurement Timer (SMT):
24-bit timer/counter with
prescaler
Several modes of operation
like Time-of-Flight, Period and Duty Cycle measurement, etc.
Data Signal Modulator (DSM):
Multiplex two carrier clocks,
with glitch prevention feature
Multiple sources for each
carrier
Programmable CRC with Memory Scan:
Reliable data/program memory
monitoring for Fail-Safe operation (e.g., Class B)
Calculate 32-bit CRC over any
portion of Program Flash Memory
Three UART modules:
One module (UART1) supports
LIN host and client, DMX mode, DALI gear and device protocols
Asynchronous UART, RS-232,
RS-485 compatible
Automatic and user timed
BREAK period generation
Automatic checksums
Programmable 1, 1.5, and two
Stop bits
Wake-up on BREAK
reception
DMA compatible
Two SPI modules:
Configurable length
bytes
Arbitrary length data
packets
Transmit-without-receive and
receive-without-transmit option
Transfer byte counter
Separate transmit and receive
buffers with 2-byte FIFO and DMA capabilities
One I2C module, SMBus,
PMBus™ Compatible:
Supports Standard-mode (100
kHz), Fast-mode (400 kHz) and Fast-mode plus (1 MHz) modes of operation
7-bit and 10-bit addressing
modes with address masking modes
Dedicated address, transmit
and receive buffers and DMA capabilities
Bus collision detection with
arbitration
Bus time-out detection and
handling
I2C, SMBus 2.0 and
SMBus 3.0, and 1.8V input level selections
Separate Transmit and Receive
Buffers with 2-byte FIFO and DMA capabilities
Multi-Master mode, including
self-addressing
Device I/O Port Features:
12 I/O pins
(PIC18F04/05/06Q40)
18 I/O pins
(PIC18F14/15/16Q40)
Individually programmable I/O
direction, open-drain, slew rate and weak pull-up control
Interrupt-on-change on most
pins
Three programmable external
interrupt pins
Peripheral Pin Select (PPS):
Enables pin mapping of
digital I/O
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.