2 Temporal Separation Measurement

The temporal separation is measured in the FPGA fabric logic that runs at a 125 MHz clock. When an awvalid rising edge is detected on either one of the FIC interfaces, a 64-bit counter is started. This counter keeps counting until the awvalid pulse is detected on the other FIC. This counter value is read by E51 through the APB interface, which is the actual temporal separation. The counter values are reset back to 0 again until the next awvalid pulse arrives on either one of the FIC interfaces. The following timing diagram shows the temporal difference between two awvalid signals in an ideal scenario. The temporal separation may vary based on the application.