1 Waypointing Implementation

The following block diagram shows the waypointing method. The E51 processor core copies the same application into two different regions of the target memory (LPDDR4/LIM/Scratchpad) for U54 processor cores. U54_1 and U54_2 are held in wait for interrupt (WFI) mode after reset. E51 requests the fabric logic to generate two interrupts to release the U54 processor cores from WFI mode. The U54_1 and U54_2 processor core execution is separated temporally by 50 µs. The temporal separation delay is application dependent. U54_1 writes incremented data pattern to a fabric register accessible at address 0x61000000 periodically (at every 100 µs) through the FIC0 interface. U54_2 writes incremented data pattern to a fabric registers accessible at address 0xE1000000 periodically (at every 100 µs) through the FIC1 interface. The periodic AXI writes from the processor must be greater than the temporal separation value. The time difference between the two AXI write (awvalid) signals is sent to the E51 processor using fabric logic through the FIC3 APB interface. The fabric logic compares the data and measures the temporal separation between the two processor writes. The E51 processor core reads the same.

The waypointing is implemented using CoreMark application. The code, data, and stack are placed in the target memory. The target memory can be LIM, ScratchPad, or LPDDR4.