3 Results

The temporal separation was measured in the fabric while executing the applications from different target memories (LIM/Scratchpad/LPDDR4). The data from the two processors is equal and the measured temporal separation is constant with a few fabric clock cycles deviation with respect to expected temporal separation. The fabric is operating at 125 MHz.

The following table lists the clock cycle deviation with respect to expected temporal separation. The same clock cycles deviation is observed with a temporal delay of 50 µs and 5 ms between the processors.

Table 3-1. Clock Cycles Deviation with respect to Expected Temporal Separation
Target MemoryClock Cycles Deviation
CodeData and StackCoreMark Application
LPDDR4LPDDR4±10
ScratchPadScratchPad ±10
LIMScratchPad±10
LIMLIM±150 1
Note:
  1. This deviation is expected due to the bus contention while accessing LIM simultaneously from more than one application core. When executing applications from LIM, the instructions and data are not cached.