6 Appendix 5: References
(Ask a Question)The following documents provide more information about the SmartDebug and IP cores used in the reference design:
- For more information about SmartDebug, see SmartDebug User Guide.
- For more information about PolarFire transceiver blocks, see PolarFire Family Transceiver User Guide .
- Fore more information about PF_CCC, see PolarFire Family Clocking Resources User Guide .
- For more information about Libero SoC, see the Libero SoC Documentation web page.
- For more information about PolarFire FPGA Evaluation Kit, see UG0747: PolarFire FPGA Evaluation Kit User Guide .
- For more information about PF_UPROM, PF_USRAM, and PF_DPSRAM, see Libero catalog.
- For more information about Identify RTL, see Synopsys Identify RTL User Guide.