AN4594

7 Revision History

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The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the current publication.

Table 7-1. Revision History
Revision	Date	Description
C	07/2025	The following is the list of changes in revision B of the document: Updated the document for Libero® v2025.1. Updated the `.job` filepath and TCL script filepath throughout the document. Updated Figure 1-7 in the Simulation Using Micron DDR4 SDRAM Model section. Updated Figure 1-11 in the Enabling FPGA Hardware Breakpoint (FHB) section.
B	08/2024	The following is the list of changes in revision B of the document: Updated the document for Libero SoC v2024p1 Updated the Figure 1-9 in the section Clocking Structure Updated the Figure 1-10 in the section Reset Structure Updated the Figure 1-13 in the section Programming the Device Updated the Figure 1-15 in the section Launch SmartDebug from Libero Updated the Figure 1-16 in the section View Device Status Updated the Figure 1-18 in the section Active Probes Updated the Figure 1-21 and Figure 1-22 in the section Memory Blocks Updated the Figure 1-24 in the section Use Event Counter Updated the Figure 1-25 in the section Use Frequency Monitor Updated the Figure 1-26 in the section Use User Clock Frequency Updated the Figure 1-27 and Figure 1-28 in the section Select FHB Updated the Figure 1-35 in the section sNVM Debug Updated the Figure 1-38 in the section Configuration Report Updated the Figure 1-39 in the section SmartBERT Updated the Figure 1-41 in the section Static Pattern Transmit Updated the Figure 1-43 in the section Eye Monitor Updated the Figure 1-50 in the section Eye Monitor after Optimizing Receiver Updated the Figure 4-6 in the section Appendix 3: Place and Route Updated the Figure 5-1 in the section Appendix 4: Running the TCL Script Added the Appendix 2 : Synthesis section
A	08/2022	The following is the list of changes in revision A of the document: The document was migrated to Microchip template. The document number was updated to DS00004594A from 51900479. The document ID was updated to AN4594 from AC479. Updated note in Memory Blocks. Updated sNVM Debug steps in sNVM Debug. Updated Loopback mode steps in Loopback Modes. Updated Signal Integrity. Updated place and route steps in Appendix 3: Place and Route.
8.0	_	The following is a summary of the changes made in this revision. Updated for Libero SoC v2021.2. Updated Design Requirements. Updated DDR Interface in Demo Design. Updated Clocking Structure and Reset Structure. Updated Enabling FPGA Hardware Breakpoint (FHB). Updated Programming the Device. Added information about applying eye mask on plotted eye diagram, see Eye Monitor. Added Register Access and Start Record Actions. Added Debug DDR IO Margin.
7.0	_	Added Appendix 4: Running the TCL Script.
6.0	_	The following is a summary of the changes made in this revision. Updated the document for Libero® SoC v12.2. Removed the references to Libero version numbers.
5.0	_	The following is a summary of the changes made in this revision. Updated the document for Libero® SoC v12.0. The new FHB feature of SmartDebug was added, see Using FHB. Updated the supported Eye Scan Modes in Eye Monitor.
4.0	_	The following is a summary of the changes made in this revision. Converted this document from a tutorial (TU0804) to an application note (AC479). Updated the document for both Evaluation and SPLASH kits. Included the information from UG0743: PolarFire FPGA Debug User Guide. Updated the document for Libero® SoC PolarFire v2.3.
3.0	_	The document was updated for Libero SoC PolarFire v2.2.
2.0	_	The document was updated for Libero SoC PolarFire v2.1.
1.0	_	The first publication of this document.

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