38.17 ADC

Table 38-24. ADC Accuracy Specifications
Operating Conditions:
  • VDD = VDDIO2 = 3.0V
  • TA = 25ºC
Symbol Description Min. Typ. ✝ Max. Unit Conditions
NR Resolution — — 12 bit
EINL Integral nonlinearity error — 0.1 — LSb VDD = VADCREF = 3.0V
EDNL Differential nonlinearity error(1) — 0.1 — LSb VDD = VADCREF = 3.0V
EOFF Offset error — 1.25 — LSb VDD = VADCREF = 3.0V
EGAIN Gain error — 2.5 — LSb VDD = VADCREF = 3.0V
EABS Absolute error — 4 — LSb VDD = VADCREF = 3.0V
VADCREF ADC reference voltage 1.8 — VDD V
VAIN Full-scale range GND — VADCREF V
RIN Input resistance — 1 — kΩ
CIN Input capacitance — 7 — pF
RVREFA ADC voltage reference ladder impedance(2) — 50 — kΩ

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Note:
  1. The ADC conversion result never decreases with an increase in the input and has no missing codes.
  2. The impedance seen by the VREFA pin when the external reference is selected.
Table 38-25. ADC Conversion Timing Specifications
Symbol Description Min. Typ. ✝ Max. Unit Conditions
TCLK_ADC * ADC clock period 0.5 — 8 μs
tCNV Conversion time — 13.5TCLK_ADC + 2TCLK_PER —
tACQ Acquisition time — 2TCLK_ADC — μs
fADC * Sample rate 8 — 130 ksps
tS Sampling time — 2TCLK_ADC —
tSENSE * Delay for changing MUXPOS to TEMP — 40 — μs
tADC_INIT * Initialization time — 6 — μs

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

* These parameters are characterized but not tested in production.