2.1 General Description
The Microchip LAN8650/1 is a 32-pin, stand-alone Ethernet Controller which includes a 10BASE‑T1S Ethernet physical layer transceiver (PHY), a Medium Access Controller (MAC) and an industry standard Serial Peripheral Interface (SPI) to enable low-cost microcontrollers to support standard networking software stacks over one inexpensive balanced pair of conductors. A block diagram is shown below.
The 10BASE‑T1S PHY is designed according to the IEEE Std 802.3cgTM-2019 specification and provides 10 Mbit/s half‑duplex transmit and receive capability over a single balanced pair of conductors such as Unshielded Twisted Pair (UTP) cable. It allows for the creation of both half‑duplex multidrop and point-to-point network topologies. Point-to-point link segments of up to at least 15m in length are supported. The multidrop mode can support up to at least 8 nodes on one mixing segment, which can be up to at least 25m long. The ability to connect multiple PHYs to a common mixing segment reduces weight and implementation costs by reducing cabling, connectors and switch ports.
The LAN8650/1 includes an Ethernet MAC to enable low-cost microcontrollers to communicate over 10BASE‑T1S via an ordinary SPI interface; there is no need for an on-chip MAC or a high pin count MII. The MAC is 802.3 compliant and includes frame filtering to limit incoming packets.
A host microcontroller communicates with the MAC using a SPI port, according to the OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface specification, which describes not only transfer of Ethernet data, but also configuration and management of control and status registers. The LAN8650/1 can accommodate a SPI clock of up to 25 MHz. The host controller can receive an interrupt from the LAN8650/1 or trigger a reset via the reset pin.
Access to the physical medium is managed by CSMA/CD and optionally supplemented by Physical Layer Collision Avoidance (PLCA) in which the LAN8650/1 may be configured with up to 9 transmit opportunities in each bus cycle. Additionally, Application Controlled Media Access (ACMA) allows implementation of time-division multiple access (TDMA) to the physical media.
Microchip’s LAN8650/1 EtherGREEN energy efficient technology provides low power 10BASE‑T1S PHY operation along with an ultra-low power sleep mode with flexible wake options.
Advanced PHY diagnostics are provided, which enable troubleshooting and monitoring capabilities such as cable defect detection of shorts or opens, a receiver Signal Quality Indicator (SQI), PLCA diagnostics, over-temperature, under-voltage detection, comprehensive status interrupt support, and various loopback and test modes.
In addition, the LAN8650/1 can be used to implement high-precision clock synchronization. This enables implementation of the IEEE Std 802.1AS profile, among others, of IEEE Std 1588 for applications utilizing AVB or other Time Sensitive Networking (TSN) standards.
An internal timestamp wallclock enables time stamping frame ingress and egress as described in the OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface specification. This clock can be used for time stamping external events or for generating synchronized pulses using the internal event generator. The device also contains a phase adjuster, which enables smoother clock adjustments with fewer controller write accesses. The reference clock can either be derived from the local crystal or provided by an external source.
The LAN8650/1 is designed to be used in ISO 26262 Functional Safety applications. A Functional Safety Package is available, including Safety Manual; Failure Modes, Effects, and Diagnostic Analysis (FMEDA); and Dependent Failure Analysis (DFA). Please contact Microchip support for additional information.
The LAN8651 includes an integrated low-dropout (LDO) regulator to simplify designs where only 3.3V supplies are available.