8.2 Page Write
A page write sequence allows up to 8 bytes to be written in the same write cycle, provided that all bytes are in the
same row of the memory array. Partial page writes of less than 8 bytes are allowed. After each byte of data is received, the three lowest order address bits are internally
incremented following the receipt of each data byte. The higher order address bits are not
incremented and retain the memory array page location. If more bytes of data are
transmitted than will fit to the end of that memory row, the address counter will roll over
to the beginning of the same row. Nevertheless, creating a rollover event should be avoided
as previously loaded data in the page could become unintentionally altered. The AT25010B/AT25020B/AT25040B is automatically returned to the Write
Disable state (WEL = 0) at the completion of a write cycle.
- This instruction initiates a self‑timed internal write cycle (tWC) on the rising edge of CS after a valid sequence.
- “A” represents the MSb address bit (A8) for the AT25040B and a “don’t care” bit for the AT25010B and AT25020B.
