1.1 Calibration

PLLs present in the fabric CCC in the RTG4 family might loose ‘LOCK’ at high temperatures. Review Customer Notifications19009A for more information.

In the CCC, ‘loss of PLL lock’ issue is addressed using soft logic that is added as part of the RTG4 FCCCECALIB generated circuit. The soft logic performs calibration at power-up or when the CCC is reset to ensure that the PLL lock is stable during the normal operation.

Internally, controller core, CorePLL_ELOCK, writes the PLL registers through the APB interface. The register values are chosen such that the high VCO values are written first, wait for 150 us and then writes the Actual VCO values.

High VCO is chosen such that the value is in the range from 1.5 to 1.9 times of the actual VCO.

If both the CCCs are used in the design, then the CCC_0 registers is loaded first followed by the CCC_1 registers.