25.8.1 TWBR – TWI Bit Rate
Register
When using the I/O specific commands IN and OUT, the I/O
addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD
and ST instructions, 0x20 must be added to these offset addresses.
| Name: | TWBR |
| Offset: | 0x00 |
| Reset: | 0x00 |
| Property: | When addressing I/O Registers as
data space the offset address is 0x20 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | TWBRn[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – TWBRn[7:0] TWI Bit Rate Register [n = 7:0]
TWBR selects the
division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See Bit Rate Generator Unit for calculating bit
rates.
