2.9.1.9.1 NAND Flash Boot: NAND Flash Detection

After the NAND Flash interface configuration, a reset command is sent to the memory.

The reset time of the NAND memory, after this reset command, must not be higher than 100 µs.

Hardware ECC detection and correction are provided by the PMECC. Refer to the section Static Memory Controller (SMC) for more details.

The ROM code retrieves NAND Flash parameters and ECC requirements using the configuration field found in the Boot Configuration Packet (refer to MEM_CFG[1]).

Once the ROM code has the ECC parameters, it configures the PMECC peripheral according to the usePmecc parameter. The image to be loaded must be at address 0x0.