2.9.1.7.17 NAND Flash Memory Boot Configuration (Second Word)
This word is the second word used to add an external NAND Flash memory in the boot sequence. It allows to inform the ROM Code the PMECC configuration to apply.
Name: | MEM_CFGx[1] |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
key[3:0] | eccOffset[8:6] | ||||||||
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
eccOffset[5:0] | sectorSize[1:0] | ||||||||
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
eccBitReq[2:0] | spareSize[8:4] | ||||||||
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
spareSize[3:0] | nbSectorPerPage[2:0] | usePmecc | |||||||
Access | |||||||||
Reset |
Bits 31:28 – key[3:0] Value 0xC Must be Written here to Validate the Content of the Whole Word
Bits 26:18 – eccOffset[8:0] Offset of the First ECC Byte in the Spare Zone (OOB)
Bits 17:16 – sectorSize[1:0] Size of the ECC Sector
Value | Description |
---|---|
0 | For 512 bytes |
1 | For 1024 bytes per sector |
Other values | For future use |
Bits 15:13 – eccBitReq[2:0] Number of ECC Bits Required
Value | Description |
---|---|
0 | 2-bit ECC |
1 | 4-bit ECC |
2 | 8-bit ECC |
3 | 12-bit ECC |
4 | 24-bit ECC |
Bits 12:4 – spareSize[8:0] Size of the Spare Zone in Bytes
Bits 3:1 – nbSectorPerPage[2:0] Number of Sectors per Page
Value | Description |
---|---|
0 | 1 sector per page |
1 | 2 sectors per page |
2 | 4 sectors per page |
3 | 8 sectors per page |
4 | 16 sectors per page |
Bit 0 – usePmecc Use PMECC
Value | Description |
---|---|
0 | Do not use PMECC to detect and correct the data. |
1 | Use PMECC to detect and correct the data. |