9.4.6.9.10 Instruction Frame Transmission Examples

All waveforms in the following examples describe SPI transfers in SPI Clock mode 0 (QSPI_SCR.CPOL = 0 and QSPI_SCR.CPHA = 0. See Serial Clock Phase and Polarity).

Example 1:

Instruction in Single-bit SPI, without address, without option, without data.

Command: CHIP ERASE (C7h).

  • Write 0x0000_00C7 in QSPI_WICR.
  • Write 0x0000_0010 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Write QSPI_CR.STTFR to 1.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-174. Instruction Transmission Waveform 1

Example 2:

Instruction in Quad SPI, without address, without option, without data.

Command: POWER DOWN (B9h)

  • Write 0x0000_00B9 in QSPI_WICR.
  • Write 0x0000_0016 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Write QSPI_CR.STTFR to 1.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-175. Instruction Transmission Waveform 2

Example 3:

Instruction in Single-bit SPI, with address in Single-bit SPI, without option, without data.

Command: BLOCK ERASE (20h)

  • Write the address (of the block to erase) in QSPI_IAR.
  • Write 0x0000_0020 in QSPI_WICR.
  • Write 0x0000_0030 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Write QSPI_CR.STTFR to 1.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-176. Instruction Transmission Waveform 3

Example 4:

Instruction in Single-bit SPI, without address, without option, with data write in Single-bit SPI.

Command: SET BURST (77h)

  • Write 0x0000_0077 in QSPI_WICR.
  • Write 0x0000_0090 in QSPI_IFR.
  • Write QSPI_WRACNT.NBWRA with the number of bytes to write.
  • Update configuration (see Updating the QSPI Configuration).
  • Write data in the system bus memory space (0x20000000 - 0x30000000) for QSPI0 or (0x30000000 - 0x40000000) for QSPI1.
The address of system bus write accesses is not used.
  • Wait for QSPI_ISR.LWRA to rise.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-177. Instruction Transmission Waveform 4

Example 5:

Instruction in Single-bit SPI, with 24-bit address in Dual SPI, without option, with data write in Dual SPI.

Command: BYTE/PAGE PROGRAM (02h)

  • Write 0x0000_0002 in QSPI_WICR.
  • Write 0x0000_18B3 in QSPI_IFR.
  • Write QSPI_WRACNT.NBWRA with the number of bytes to write.
  • Update configuration (see Updating the QSPI Configuration).
  • Write data in the QSPI system bus memory space (0x20000000 - 0x30000000) for QSPI0 or (0x30000000 - 0x40000000) for QSPI1.
The address of the first system bus write access is sent in the instruction frame.
The address of the next system bus write accesses is not used.
  • Wait for QSPI_ISR.LWRA to rise.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-178. Instruction Transmission Waveform 5

Example 6:

Instruction in Single-bit SPI, with 24-bit address in Single-bit SPI, without option, with data read in Quad SPI, with eight dummy cycles.

Command: QUAD_OUTPUT READ ARRAY (6Bh)

  • Write 0x0000_006B in QSPI_RICR.
  • Write 0x0008_18B2 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Read data in the QSPI system bus memory space (0x20000000 - 0x30000000) for QSPI0 or (0x30000000 - 0x40000000) for QSPI1.
The address of the first system bus read access is sent in the instruction frame.
The address of the next system bus read accesses is not used.
  • Wait for QSPI_SR.RBUSY=0 and QSPI_SR.HIDLE=1.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-179. Instruction Transmission Waveform 6

Example 7:

Instruction in Single-bit SPI, with 24-bit address and option in Quad SPI, with data read in Quad SPI, with four dummy cycles and continuous read.

Command: FAST READ QUAD I/O (EBh) - 8-BIT OPTION (0x30h)

  • Write 0x0030_00EB in QSPI_RICR.
  • Write 0x0004_1BF4 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Read data in the QSPI system bus memory space (0x20000000 - 0x30000000) for QSPI0 or (0x30000000 - 0x40000000) for QSPI1.
The address of the system bus read accesses is always used.
  • Wait for QSPI_SR.RBUSY=0 and QSPI_SR.HIDLE=1.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-180. Instruction Transmission Waveform 7

Example 8:

Instruction in Quad SPI, with 24-bit address in Quad SPI, without option, with data read in Quad SPI and two dummy cycles.

Command: HIGH-SPEED READ (0Bh)

  • Write 0x0000_000B in QSPI_RICR.
  • Write 0x0002_08B6 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Read data in the QSPI system bus memory space (0x20000000 - 0x30000000) for QSPI0 or (0x30000000 - 0x40000000) for QSPI1.
The address of the system bus read accesses is always used.
  • Wait for QSPI_SR.RBUSY=0 and QSPI_SR.HIDLE=1.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-181. Instruction Transmission Waveform 8

Example 9:

Instruction in Quad SPI, without address, without option, with data read in Quad SPI, without dummy cycles, without fetch.

Command: Read Status register (05h)

  • Write 0x0000_0005 in QSPI_RICR.
  • Write 0x0000_0096 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Read data in the QSPI system bus memory space (0x20000000 - 0x30000000) for QSPI0 or (0x30000000 - 0x40000000) for QSPI1.
Fetch is disabled.
  • Wait for QSPI_SR.RBUSY=0 and QSPI_SR.HIDLE=1.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-182. Instruction Transmission Waveform 9

Example 10:

Instruction in Quad SPI, without address, without option, with data read in Quad SPI, without dummy cycles, and read launched through the peripheral bus.

Command: Read Status register (05h)

  • Set SMRM to 1 and TFRTYP to 0 in QSPI_MR
  • Write 0x0000_0005 in QSPI_RICR.
  • Write 0x0100_0096 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Write a 1 to QSPI_CR.STTFR.
  • Wait for flag RDRF and Read data in QSPI_RDR.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
  • Read data in QSPI_RDR.
Figure 9-183. Instruction Transmission Waveform 10

Example 11:

Instruction in Octal Twin-Quad SPI, with 24-bit address in Octal Twin-Quad SPI, without option, with data read in Octal Twin-Quad SPI and two dummy cycles.

Command: HIGH-SPEED READ (0Bh)

  • Write 0x0000_000B in QSPI_RICR.
  • Write 0x1002_18B9 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Read data in the QSPI system bus memory space (0x20000000 - 0x30000000) for QSPI0 or (0x30000000 - 0x40000000) for QSPI1.
The address of the system bus read accesses is always used.
  • Wait for QSPI_SR.RBUSY=0 and QSPI_SR.HIDLE=1’.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-184. Instruction Transmission Waveform 11

Example 12:

Instruction in Octal Twin-Quad SPI, without address, without option, with data read in Octal Twin-Quad SPI, without dummy cycles and read launched through the peripheral bus.

Command: Read Status register (05h)

  • Write a 1 to QSPI_MR.SMRM and a 0 to TFRTYP.
  • Write 0x0000_0005 in QSPI_RICR.
  • Write 0x1100_0099 in QSPI_IFR.
  • Update configuration (see Updating the QSPI Configuration).
  • Write a 1 to QSPI_CR.STTFR.
  • Wait flag RDRF and Read data in the QSPI_RDR register.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
  • Read data in the QSPI_RDR register.
Figure 9-185. Instruction Transmission Waveform 12

Example 13:

Classic HyperFlash command. Instruction in Octal DDR SPI, HyperFlash mode, without option, with data write, without dummy cycles and write launched through the peripheral bus.

Command: Data 0xAA at address 0x555

  • Write 0x36C0_8099 in QSPI_IFR.
  • Write 0x555 to QSPI_IADR.
  • Update configuration (see Updating the QSPI Configuration).
  • Wait QSPI_ISR.TDRE Flag
  • Write 0xAA to QSPI_TDR.
  • Wait QSPI_ISR.TXEMPTY Flag.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-186. Instruction Transmission Waveform 13

Example 14:

Classic HyperFlash command. Instruction in Octal DDR SPI, HyperFlash mode, without option, with data write, without dummy cycles, without fetch, write launched through the system bus interface.

Command: Data 0xAA at address 0x555

  • Write 0x3640_8099 in QSPI_IFR.
  • Write 0x01 in QSPI_WRACNT
  • Update configuration (see Updating the QSPI Configuration).
  • Write data 0xAA (byte access) in the QSPI system bus memory space with LSB address bytes=0x555 (0x20000000 - 0x30000000) for QSPI0 or (0x30000000 - 0x40000000) for QSPI1.
  • Wait for QSPI_ISR.LWRA to rise.
  • Write a 1 to QSPI_CR.LASTXFR.
  • Wait for QSPI_ISR.CSRA to rise.
Figure 9-187. Instruction Transmission Waveform 14