2.2.3.2.2 DMA Channel QoS

  • Each channel QoS is configured through a 2-bit wide register: XDMAC_CNDC[channel number].qos.
  • The 2-bit XDMAC_CNDC[channel number].qos value is duplicated to form a 4-bit bus that connects XDMAs to the UDDRC through the interconnect, therefore not all 4-bit QoS values are available.

    Possible values = {0, 0x5, 0xA, 0xF}.

  • The XDMAC_CNDC[channel number].qos is only used by the following DMA transactions:
    • Read New Descriptor
    • Write Last Burst of Data before Reading New Descriptor
  • For all other DMA transfers, the 4-bit QOS is 0 (lowest priority).
Register fields:
  • XDMAC_CNDC[channel_number].qos = 3 for channel_number in [31:0] for XDMA0
  • XDMAC_CNDC[channel_number].qos = 3 for channel_number in [31:0] for XDMA1
  • XDMAC_CNDC[channel_number].qos = 0 for channel_number in [7:0] for XDMA2