9.8.7.50 PWM External Trigger Register
This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register.
| Name: | PWM_ETRGx |
| Offset: | 0x042C + (x-1)*0x20 [x=1..2] |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RFEN | TRGSRC | TRGFILT | TRGEDGE | TRGMODE[1:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MAXCNT[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MAXCNT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MAXCNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – RFEN Recoverable Fault Enable
| Value | Description |
|---|---|
| 0 |
The TRGINx signal does not generate a recoverable fault. |
| 1 |
The TRGINx signal generate a recoverable fault in place of the fault x input. |
Bit 30 – TRGSRC Trigger Source
| Value | Description |
|---|---|
| 0 |
The TRGINx signal is driven by the PWMEXTRGx input. |
| 1 |
Bit 29 – TRGFILT Filtered input
| Value | Description |
|---|---|
| 0 |
The external trigger input x is not filtered. |
| 1 |
The external trigger input x is filtered. |
Bit 28 – TRGEDGE Edge Selection
| Value | Name | Description |
|---|---|---|
| 0 | FALLING_ZERO |
TRGMODE = 1: TRGINx event detection on falling edge. TRGMODE = 2, 3: TRGINx active level is 0 |
| 1 | RISING_ONE |
TRGMODE = 1: TRGINx event detection on rising edge. TRGMODE = 2, 3: TRGINx active level is 1 |
Bits 25:24 – TRGMODE[1:0] External Trigger Mode
| Value | Name | Description |
|---|---|---|
| 0 | OFF |
External trigger is not enabled. |
| 1 | MODE1 |
External PWM Reset Mode |
| 2 | MODE2 |
External PWM Start Mode |
| 3 | MODE3 |
Cycle-by-cycle Duty Mode |
Bits 23:0 – MAXCNT[23:0] Maximum Counter value
Maximum channel x counter value measured at the TRGINx event since the last read of the register.
At the TRGINx event, if the channel x counter value is greater than the stored MAXCNT value, then MAXCNT is updated by the channel x counter value.