6.2.6.3.5 Frame Buffer DMA Address Alignment Requirements

When programming the Frame Buffer registers of each layer (LCDC_xxxFBA), the following requirements must be met:

Table 6-3. Frame Buffer DMA Address Alignment when CLUT Mode is Selected
CLUT ModeDMA Address Alignment
1 bpp8 bits
2 bpp8 bits
4 bpp8 bits
8 bpp8 bits
Table 6-4. Frame Buffer DMA Address Alignment when RGB Mode is Selected
RGB ModeDMA Address Alignment
12 bpp RGB 44416 bits
16 bpp ARGB 444416 bits
16 bpp RGBA 444416 bits
16 bpp RGB 56516 bits
16 bpp ARGB 155516 bits
18 bpp RGB 66632 bits
18 bpp RGB 666 PACKED8 bits
19 bpp ARGB 166632 bits
19 bpp ARGB 1666 PACKED8 bits
24 bpp RGB 88832 bits
24 bpp RGB 888 PACKED8 bits
25 bpp ARGB 188832 bits
32 bpp ARGB 888832 bits
32 bpp RGBA 888832 bits
Table 6-5. Frame Buffer DMA Address Alignment when YCbCr Mode is Selected
YCbCr ModeDMA Address Alignment
32 bpp AYCbCr32 bits
16 bpp YCbCr 4:2:232 bits
16 bpp semiplanar YCbCr 4:2:2Y 8 bits
CbCr 16 bits
16 bpp planar YCbCr 4:2:2Y 8 bits
Cb 8 bits
Cr 8 bits
12 bpp semiplanar YCbCr 4:2:0Y 8 bits
CbCr 16 bits
12 bpp planar YCbCr 4:2:0Y 8 bits
Cb 8 bits
Cr 8 bits