ULP0 Mode Operation

ULP0 mode maintains very low frequency clocks (MCK1, CPU_CLK) in the system to wake up on any interrupt. Selection of the clock frequency depends on the current consumption target versus the required wake-up time. The higher the frequency, the higher the power consumption and the faster the wake-up time.

The sequence to enter ULP0 mode is detailed below. The code used to enter this mode must be executed out of the internal SRAM. Steps 1 to 6 are meant to bypass the DDR delay lines so as to avoid their power consumption.

Entering ULP0 Mode

  1. Enter SDRAM Self-refresh mode (if used).
  2. Turn on DDR PLL (if DDR was not used).
  3. Reset the DDR Controller using RSTC_GRSTR.
  4. Wait until the status bit is asserted.
  5. Program the lane and control delay lines bypass using the DDLDIS bit in DDR3PHY_ACDLLCR, DDR3PHY_DX0DLLCR and DDR3PHY_DX1DLLCR registers.
  6. Turn off DDRPLL in PMC.
  7. Set the interrupts to wake up the system.
  8. Disable all peripheral clocks.
  9. Set the I/Os to an appropriate state and suspend the USB transceivers.
  10. Switch the system clock to MD_SLCK.
  11. Disable the PLLs, the Main Crystal Oscillator and the Main RC Oscillator.
  12. Enter the Wait for Interrupt (WFI) mode.

Exiting ULP0 Mode

Wake-up from ULP0 mode is triggered by any enabled interrupt. When resuming, the software reconfigures the system (oscillator, PLL, etc.) to the same state as before WFI. The Analog LDO must be set back to normal mode.