2.3.9 System Counter and Generic Timer

The system counter is a free-running counter that increments at a fixed frequency. GCLK28 is the source clock for the system counter. It is running and is configured to use MAINCK with no divider at reset.

The value of the counter is broadcast to the generic timer located in the CPU core.

The generic timer can schedule events and trigger interrupts based on the system counter value. It provides:
  • Generation of timer events as interrupt outputs
  • Generation of event streams
  • Support for virtualization extensions

The Coresight 400 IP is memory-mapped into APB_DEBUG_S (0xE8800000) and the system counter registers are at an offset of 0x43000.

To generate a timer interrupt:
  1. Access the memory map interface of the System Counter module(1) and:
    1. Set the system counter frequency value to 24 MHz by writing 24000000 to the CNTFID0 register (same as the MAINCK frequency).
    2. Enable the System Counter by writing 1 to the CNTCR register.
  2. Enable PPI interrupt ID29 in GIC (secure physical timer interrupt)(2).
  3. Access the generic timer coprocessor interface (CP15)(3) in order to:
    1. set the counter frequency value to 24 MHz in the CNTFRQ register,
    2. set the timer count value in the CNTP_TVAL register,
    3. enable the Timer event by writing into the CNTP_CTL register.
Note:
  1. Refer to ARM V7A ARCH Manual (DDI0406C), Appendix D5.2, Coresight 400 TRM (DDI0480G), Section 3.19.
  2. Refer to Cortex™-A7 TRM (DDI0464F), Section 8.2.2.
  3. Refer to ARM V7A ARCH Manual (DDI0406C), B8.2.
Warning: The system counter is enabled and disabled with the JTAG interface. Check the status of the JTAGDIS bitfield in the OTPC_UHC0R register to check whether it can be used or not.