9.7.5.4.2 Clock Stalling Conditions
The I3CC stalls I3CC_SCL clock during specific scenarios of non-HDR transfers. This is to accommodate intermittent system latencies during command pipelining, transmit data pre-fetching, response reading, and so on. The I3CC also provides additional options in the form of Start Thresholds and Buffer Thresholds to avoid clock stalling.
Clock stalling is a feature that helps avoid overrun and underrun errors when the I3CC is in SDR mode.
| Transfer Command | Previous Command Condition | Condition to Enter Clock Stalling |
|---|---|---|
| I3C/I2C Transfer, ACK/NACK Phase | ||
| Write Transfer Regular command | TOC bit set to '0' | Transmit FIFO is empty |
| Read Transfer Regular command | TOC bit set to '0' | Receive FIFO is full |
| Follow-up Directed CCC command without payload (Immediate/Regular) (Not 1st Directed CCC command) | Previous Directed CCC command, TOC bit set to '0' | CMD-QUEUE is empty. |
| Broadcast CCC Transfer with Regular command | TOC bit set to '0' | Transmit FIFO is empty |
| Directed CCC Write Transfer Regular command | TOC bit set to '0' | Transmit FIFO is empty |
| Directed CCC Read Transfer Regular command | TOC bit set to '0' | Receive FIFO is full |
| Directed CCC command without Payload and ROC bit is set to '1' | TOC bit set to '0' | RESP-Queue is full |
| Middle of I2C Write Transfer with Regular Transfer command | NA | Transmit FIFO is empty |
| Middle of I2C Read Transfer with Regular Transfer command | NA | Receive FIFO is full |
| End of I2C Write Transfer Regular command (Only I3CC Terminates) and TOC bit set to '0'. | NA | Next command unavailable |
| End of I2C Write Transfer Regular command (Only I3CC Terminates) and ROC bit is set to '1'. | NA | RESP-Queue is full |
| End of I2C Read Transfer Regular command (Either I3CC/target terminates) and TOC bit set to '0'. | NA | Next command unavailable |
| End of I2C Read Transfer Regular command (Only I3CC Terminates) and ROC bit is set to '1'. | NA | RESP-Queue is full |
| Write Data Transfer, Parity Bit | ||
| Middle of Write Transfer Regular command | NA | Transmit FIFO is empty |
| End of Write Transfer Regular command (Only I3CC Terminates) and TOC bit set to '0'. | NA | Next command unavailable |
| End of Write Transfer Regular command (Only I3CC Terminates) and ROC bit is set to '1'. | NA | RESP-Queue is full |
| I3C Read Transfer, Transition Bit | ||
| Middle of Read Transfer Regular command | NA | Receive FIFO is full |
| End of Read Transfer Regular command (Either I3CC/target terminates) and TOC bit set to '0'. | NA | Next command unavailable |
| End of Read Transfer Regular command (Only I3CC Terminates) and ROC is set to '1'. | NA | RESP-Queue is full |
| I3C IBI Transfer, Transition Bit | ||
| Middle of IBI Read Data Transfer | NA | IBI-Data FIFO is full |
| Middle of Auto Command Read Data Transfer | NA | IBI-Data FIFO is full |
The I3CC exits the clock stalling state once the condition mentioned in the column ‘Condition to Enter Clock Stalling’ column becomes invalid.