9.7.5.12.1 Overview of SCL Generation and Timings in I3CC

The I3C protocol supports three different bus configurations to determine the speed options. Bus configurations and their supported speed modes are shown in the following table.

Table 9-76. Bus Configuration and Supported Speed Modes
Speed Mode	Bus Configuration
Speed Mode	Pure Bus (Only I3C Devices)	Mixed Fast Bus (Both I3C and I2C devices)⁽¹⁾	Mixed Slow and Limited Bus (Both I3C and I2C devices)⁽¹⁾
SDR Mode	Any speed to f_SCL (Max)	FM, FM+, f_{SCL_MIXED} (Min) to f_{SCL_MIXED} (Max), or slower using duty cycle	FM or FM+ only
HDR-DDR Mode	Yes	Yes, using f_{SCL_MIXED}, or slower using duty cycle	No

Note:

In this configuration, I2C devices do not perform clock stretching but have a glitch filter.

As indicated in the table above, the I3C Protocol Specification recommends extending the low period (varying the duty-cycle), which changes the bus frequency in Pure Bus and Mixed Fast Bus system. The high period must never exceed 45 ns (corresponding to 11 MHz clock frequency), thus staying below the 50 ns required by the I2C glitch filter; however, the low period can be of any length permitted by the I3C device's allowed clock frequency range. The extended low period can be used for certain slow I3C devices supporting lower data rate (2, 4, 6, or 8 MHz).

The timing parameters for the subsequent transfer after the Address Header/Address Phase is selected based on the mode of the transfer:

I3C Transfer: Push-Pull Timing
I2C Transfer: Open-Drain Timing

Note:

ACK for address phase of I3C transfer is always driven in Open-Drain mode.
Complete ENTDAA transfer from START condition to STOP condition is generated in I3C Open-Drain mode.