11.1.5.1 Power-Up and Power-Down

At power-up, from a power supply sequencing perspective, the SAMA7D6 power supply inputs are categorized into three independent groups:

VDDIN33,
the core group that contains VDDCPU and VDDCORE, and
the periphery group that contains all other power supply inputs except VBAT.

The following figure shows the recommended power-up sequence. Note the following:

VBAT
- When supplied from a pre-charged storage element (battery or supercapacitor), VBAT is an always-on supply input and is therefore not part of the power supply sequencing.
- When no storage element is used on VBAT in the application, VBAT must be tied to VDDIN33.
- When a supercapacitor is used in the application to power VBAT during Backup mode, this element must be isolated from VBAT during its (slow) charge so that VBAT closely follows VDDIN33. In Table 11-10, the parameter t₀ limits the delay to establish VBAT after VDDIN33.
VDDOUT25 is the output of the internal VDDOUT25 regulator, therefore, there is no power supply requirement on this pin. VDDOUT25 is mentioned in the following figures for information only. VDDOUT25 is automatically started at VDDIN33 rise when VDDIN33 is above its power-on reset threshold.
VDDDPHY, VDDIN25 and VDDANA must be connected to VDDOUT25 and are therefore not subject to any supply sequencing requirement.
VDDLVDS requirements do not apply when VDDLVDS is connected to VDDOUT25.
NRST must be asserted low during the whole power-up sequence.

Figure 11-2. Recommended Power Sequence at Power-Up

Table 11-10. Power-Up Timing Specification⁽¹⁾
Symbol	Parameter	Conditions	Min	Max	Unit
t₀	VBAT delay	Delay from established VDDIN33 to established VBAT	–	0.2	ms
t₁	VDDIN33 to periphery group delay	Delay from established VDDIN33 to the first established periphery group supply	-0.3	–	ms
t₂	Periphery group to VDDCORE delay	Delay from the last established periphery group supply to the first core group supply turn-on	0	–	ms
t₃	Reset delay at power-up	Delay from the last established core group supply to NRST high	8	–	ms

Note:

The term "established" refers to a power supply established at 90% of its final value.

The following figure shows the SAMA7D6 power-down sequence that starts by asserting the NRST line to 0. Once NRST is asserted, the supply inputs can be immediately shut down without any specific timing or order. VBAT may not be shut down if the application uses a backup storage element on this supply input. When VDDIN33 falls below the negative-going threshold of the VDDIN33 power-on reset, the VDDOUT25 regulator is automatically shut down and its output is pulled low by an internal discharge resistor.

Figure 11-3. Recommended Power Sequence at Power-Down

Table 11-11. Power-Down Timing Specification
Symbol	Parameter	Conditions	Min	Max	Unit
t_RSTPD	NRST Delay at power-down	Delay from NRST low to the first supply out of its operating range	0	–	ms