7.5.7.3 SPDIF Transmitter Extended Mode Register

This register can only be written if the WPEN bit is cleared in SPDIFTX_WPMR.

Name:	SPDIFTX_EMR
Offset:	0x08
Reset:	0x03000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	DTCEN7	DTCEN6	DTCEN5	DTCEN4	DTCEN3	DTCEN2	DTCEN1	DTCEN0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	1	1


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
				VALIDM	PARM	CSM	UDM	PCM
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 24, 25, 26, 27, 28, 29, 30, 31 – DTCENx Direct Audio Transmit Channel x Enable

The SPDIF format handles only two channels, so only two channels can be enabled. If more than two channels are enabled, only the lowest and the highest index enabled channels of the direct access audio stream are transmitted. By default, indexes 0 and 1 are enabled.

Value	Description
0	The channel x from the direct audio stream is not transmitted on the SPDIF line.
1	The channel x from the direct audio stream is transmitted on the SPDIF line.

Bit 4 – VALIDM Validity Bit Mode

Value	Description
0	Validity bit is defined by SPDIFTX_MR.VALID1 and SPDIFTX_MR.VALID2 values.
1	Validity bit is defined by SPDIFTX_CDR.VALID.

Bit 3 – PARM Parity Mode

Value	Description
0	Parity bit is automatically set by the SPDIFTX.
1	Parity bit sent is defined by SPDIFTX_CDR.PAR.

Bit 2 – CSM Channel Status Mode

Value	Description
0	Channel status is defined by SPDIFTX_CHySx.
1	Channel status is defined by SPDIFTX_CDR.CS.

Bit 1 – UDM User Data Mode

Value	Description
0	User data is defined by SPDIFTX_CHyUDx.
1	User data is defined by SPDIFTX_CDR.UD.

Bit 0 – PCM Preamble Code Mode

Value	Description
0	Preamble code is generated automatically by the SPDIFTX.
1	Preamble code is defined by SPDIFTX_CDR.PC.