7.5.7.16 SPDIF Transmitter Fault Injection Register
| Name: | SPDIFTX_FIR |
| Offset: | 0xB8 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FIKEY[23:16] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIKEY[15:8] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIKEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIRDIS | FNBR | F4 | F3 | F2 | F1 | F0 | |||
| Access | R/W | W | W | W | W | W | W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:8 – FIKEY[23:0] Fault Injection Key
| Value | Name | Description |
|---|---|---|
| 0x534649 | PASSWD | Writing any other value in this field aborts the write operation. Always reads as 0. |
Bit 7 – FIRDIS Fault Injection Register Disable
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect |
| 1 | ACTIVE | Disables the fault injection until the next hardware reset. The command is valid only if the flags SPDIFTX_WPSR.SDEE=0 and SPDIFTX_WPSR.NCE=0 and the other bits are cleared (F0=F1=F2=F3=F4=0). |
Bit 5 – FNBR Fault Number
| Value | Name | Description |
|---|---|---|
| 0 | SINGLE | One error is injected in the selected register. |
| 1 | DOUBLE | Two errors are injected in the selected register. |
Bit 4 – F4 Single Fault for Write Protection Mode Register (SPDIFTX_WPMR)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Injects a single fault in the reinforced safety for the SPDIFTX_WPMR if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The flags SPDIFTX_ISR.SECE=1, SPDIFTX_WPSR.SDEE=1. If DUAL=1, the flag SPDIFTX_WPSR.NCE=1. |
Bit 3 – F3 Single Fault for Channel Status Registers (SPDIFTX_CH1Sx/CH2Sx)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Injects a single fault in the reinforced safety for the SPDIFTX_CH1Sx/CH2Sx if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The flags SPDIFTX_ISR.SECE=1, SPDIFTX_WPSR.SDEE=1 and SPDIFTX_WPSR.NCE=1. |
Bit 2 – F2 Single Fault for User Data Registers (SPDIFTX_CH1UDx/CH2UDx)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Injects a single fault in the reinforced safety for the SPDIFTX_CH1/2UDx if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The flags SPDIFTX_ISR.SECE=1 , SPDIFTX_WPSR.SDEE=1 and SPDIFTX_WPSR.NCE=1. |
Bit 1 – F1 Single Fault for Interrupt Mask Register (SPDIFTX_IMR)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Injects a single fault in the reinforced safety for the SPDIFTX_IMR if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The flag SPDIFTX_ISR.SECE=1, SPDIFTX_WPSR.SDEE=1 and SPDIFTX_WPSR.NCE=1. |
Bit 0 – F0 Single Fault for Mode Registers (SPDIFTX_MR and SPDIFTX_EMR)
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Injects a single fault in the reinforced safety for the SPDIFTX_MR and SPDIFTX_EMR if 0x534649 (“SFI” in ASCII) is written in the FIKEY field at the same time. The flags SPDIFTX_ISR.SECE=1, SPDIFTX_WPSR.SDEE=1. If DUAL=1, the flag SPDIFTX_WPSR.NCE=1. |
