2.8.9.22 XDMAC Global Bus Error Interrupt Routing Register
| Name: | XDMAC_GBEIR |
| Offset: | 0x54 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NSBER31 | NSBER30 | NSBER29 | NSBER28 | NSBER27 | NSBER26 | NSBER25 | NSBER24 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NSBER23 | NSBER22 | NSBER21 | NSBER20 | NSBER19 | NSBER18 | NSBER17 | NSBER16 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NSBER15 | NSBER14 | NSBER13 | NSBER12 | NSBER11 | NSBER10 | NSBER9 | NSBER8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NSBER7 | NSBER6 | NSBER5 | NSBER4 | NSBER3 | NSBER2 | NSBER1 | NSBER0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – NSBERx XDMAC Channel x Non-Secure Bus Error Routing
| Value | Description |
|---|---|
| 0 | Non-secure channel x bus errors are flagged in the Channel x Interrupt Status register and they can only set the non-secure interrupt line. |
| 1 | Non-secure channel x bus errors are flagged in the secure Global Bus Error Interrupt Status register x bit and they only set the secure Interrupt line. |