2.8.9.23 XDMAC Global Bus Error Interrupt Status Register
| Name: | XDMAC_GBEIS |
| Offset: | 0x58 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| NSBES31 | NSBES30 | NSBES29 | NSBES28 | NSBES27 | NSBES26 | NSBES25 | NSBES24 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| NSBES23 | NSBES22 | NSBES21 | NSBES20 | NSBES19 | NSBES18 | NSBES17 | NSBES16 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NSBES15 | NSBES14 | NSBES13 | NSBES12 | NSBES11 | NSBES10 | NSBES9 | NSBES8 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| NSBES7 | NSBES6 | NSBES5 | NSBES4 | NSBES3 | NSBES2 | NSBES1 | NSBES0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – NSBESx XDMAC Channel x Non-Secure Bus Error Status
| Value | Description |
|---|---|
| 0 | No non-secure bus error occurred on channel x since the last read of this register or the Bus Error events are not routed to the secure interrupt in the XDMAC_GBEIR.x bit. |
| 1 | A non-secure bus error occurred on channel x since the last read of this register and the Bus Error events are routed to the secure interrupt in the XDMAC_GBEIR.x bit. |