8.9.6.9 TRNG Fault Injection Register
This register can only be written if FIRDIS is cleared.
All bits are read/write except FIRDIS.
| Name: | TRNG_FIR |
| Offset: | 0x40 |
| Reset: | – |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| FIKEY[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIKEY[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FIKEY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FIRDIS | NSFHT | FSEQE | F4 | F3 | F2 | F1 | F0 | ||
| Access | R | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 31:8 – FIKEY[23:0] Fault Injection Access Key
| Value | Name | Description |
|---|---|---|
| 0x544649 | PASSWD | Writing any other value in this field aborts the write operation. |
Bit 7 – FIRDIS Fault Injection Register Disable
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. |
| 1 | ACTIVE | Disables the fault injection until the next hardware reset. The command is valid only if TRNG_WPSR.SEQE=0 and the other bits are cleared (F0=F1=F2=F3=F4=FSEQE=NSFHT=0). |
Bit 6 – NSFHT Noise Source Failure for Health Test
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. |
| 1 | FAIL | Injects a fault on the noise source (if TRNG_CR.ENABLE=1, TRNG_ISR.RCHT=0 and TRNG_ISR.APHT=0) for a period that ends automatically as soon as TRNG_ISR.APHT=1 and TRNG_ISR.RCHT=1. For security reasons, when FIRLCK=1, writing NSFHT=1 has no effect. |
Bit 5 – FSEQE Single Fault for TRNG_MR
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. |
| 1 | INJECT_CLEAR | Injects a single fault on TRNG_MR if the TRNG is disabled (for security reasons). As a consequence, the flag TRNG_WPSR.SEQE rises and the flag TRNG_ISR.SECE=1. Clears the fault if it has been previously injected. |
Bit 4 – F4 Single Fault for TRNG Interrupt Mask Bit (TRNG_IMR.DATRDY)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag TRNG_WPSR.SDEE is automatically cleared. |
| 1 | Injects a single fault on the reinforced safety memory cell for the TRNG_IMR.WPCREN bit if 0x544649 (“TFI” in ASCII) is written in the FIKEY field at the same time. The TRNG remains in the same state, the flag TRNG_ISR.SECE=1 and the flag TRNG_WPSR.SDEE=1. |
Bit 3 – F3 Single Fault for TRNG Write Protection Bit (TRNG_WPMR.WPCREN)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag TRNG_WPSR.SDEE is automatically cleared if no other fault exists. |
| 1 | Injects a single fault on the reinforced safety memory cell for the TRNG_WPMR.WPEN bit if 0x544649 (“TFI” in ASCII) is written in the FIKEY field at the same time. The TRNG Control register remains protected, the flag TRNG_ISR.SECE=1 and the flag TRNG_WPSR.SDEE=1. |
Bit 2 – F2 Single Fault for TRNG Write Protection Bit (TRNG_WPMR.WPITEN)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag TRNG_WPSR.SDEE is automatically cleared if no other fault exists. |
| 1 | Injects a single fault on the reinforced safety memory cell for the TRNG_WPMR.WPITEN bit if 0x544649 (“TFI” in ASCII) is written in the FIKEY field at the same time. The TRNG protection remains active for interrupt registers, the flag TRNG_ISR.SECE=1 and the flag TRNG_WPSR.SDEE=1. |
Bit 1 – F1 Single Fault for TRNG Write Protection Bit (TRNG_WPMR.WPEN)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag TRNG_WPSR.SDEE is automatically cleared if no other fault exists. |
| 1 | Injects a single fault on the reinforced safety memory cell for the TRNG_WPMR.WPEN bit if 0x544649 (“TFI” in ASCII) is written in the FIKEY field at the same time. The TRNG protection remains active for Mode registers, the flag TRNG_ISR.SECE=1 and the flag TRNG_WPSR.SDEE=1. |
Bit 0 – F0 Single Fault for TRNG Enable Bit (TRNG_CR.ENABLE)
| Value | Description |
|---|---|
| 0 | Clears the fault. The flag TRNG_WPSR.SDEE is automatically cleared. |
| 1 | Injects a single fault on the reinforced safety memory cell for the TRNG_CR.ENABLE bit if 0x544649 (“TFI” in ASCII) is written in the FIKEY field at the same time. The TRNG remains in the same state, the flag TRNG_ISR.SECE=1 and the flag TRNG_WPSR.SDEE=1. |