8.9.6.2 TRNG Mode Register

This register can only be written if the WPEN bit is cleared in the TRNG Write Protection Mode Register.

Name:	TRNG_MR
Offset:	0x04
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	DIFF				HDSEL[1:0]		HD	HALFR
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0

Bit 7 – DIFF Minimum Hamming Distance

Value	Name	Description
0	DISABLED	Delivers a new random sample without condition with the previous sample (unless HD=1).
1	ENABLED	Delivers a new random sample only if it differs from the previous delivered sample (unless HD=1).

Bits 3:2 – HDSEL[1:0] Hamming Distance Selection

Value	Name	Description
0	TWO	Two consecutive random samples have a minimum Hamming distance of 2.
1	FOUR	Two consecutive random samples have a minimum Hamming distance of 4.
2	EIGHT	Two consecutive random samples have a minimum Hamming distance of 8.
3	SIXTEEN	Two consecutive random samples have a minimum Hamming distance of 16.

Bit 1 – HD Hamming Distance Check

Value	Name	Description
0	DISABLED	Delivers a new random sample without condition with the previous sample (unless DIFF=1).
1	ENABLED	Delivers a new random sample only if it meets a minimum Hamming distance with the previous delivered sample (the HDSEL field defines the minimum distance). When HD=1, DIFF has no effect.

Bit 0 – HALFR Half Rate Enable

Value	Name	Description
0	DISABLED	Maximum stream rate provided (1 sample every 84 MCK clock cycles).
1	ENABLED	Half maximum stream rate provided if the peripheral clock frequency is above 100 MHz (1 sample every 168 MCK clock cycles).

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