9.7.5.13 Derivation of I3C/I2C Timing Parameters from Timing Registers

This section describes how the timing parameters are derived from the Timing registers in different bus configurations.

Table 9-77. I3C Timing When Communication with I2C Legacy Devices⁽¹⁾
Parameter	Symbol	Legacy Mode 400 kHz/FM	Legacy Mode 1 MHz/FM+	Units	Notes
I3CC_SCL Frequency	f_SCL	1/((I2C_FM_LCNT+ I2C_FM_HCNT)*GCLK_PER)	1/((I2C_FMP_LCNT, I2C_FMP_HCNT)*GCLK_PER)	MHz	–
Setup Time for a Repeated START	t_{SU_STA}	I2C_FM_HCNT*GCLK_PER	I2C_FMP_HCNT*GCLK_PER	ns	–
Hold Time for a Repeated START	t_{HD_STA}	I2C_FM_HCNT*GCLK_PER	I2C_FMP_HCNT*GCLK_PER	ns	–
I3CC_SCL Clock Low Period	t_LOW	I2C_FM_LCNT*CCLK _PER	I2C_FMP_LCNT*GCLK_PER	ns	–
I3CC_SCL Clock High Period	t_HIGH	I2C_FM_HCNT*GCLK_PER	I2C_FMP_HCNT*GCLK_PER	ns	–
Data Setup Time	t_{SU_DAT}	(I2C_FM_LCNT- SDA_TX_HOLD)*GCLK_PER	(I2C_FMP_LCNT- SDA_TX_HOLD)*GCLK_PER	ns	Data setup is considered for the write transfer from the I3CC alone point of view. The system delays are not considered.
Data Hold Time	t_{HD_DAT}	SDA_TX_HOLD*GCLK_PER	SDA_TX_HOLD*GCLK_PER	ns	Data hold is considered for the write transfer from the I3CC alone point of view. The system delays are not considered.
Setup Time for STOP	t_{SU_STO}	I2C_FM_HCNT*GCLK_PER	I2C_FMP_HCNT*GCLK_PER	ns	–
Bus Free Time between a STOP condition and a START condition	t_BUF	I3C_HC_FREE*GCLK_PER	I3C_HC_FREE*GCLK_PER	ns	–

Note:

GCLK_PER is the period of the I3CC clock.

Table 9-78. I3C Open-Drain Timing Parameters⁽¹⁾
Parameter	Symbol	I3C Open-Drain Mode	Units	Notes
Low Period of I3CC_SCL Clock	t_{LOW_OD}	I3C_OD_LCNT*GCLK_PER	ns	–
High Period of I3CC_SCL Clock	t_HIGH	I3C_OD_HCNT*GCLK_PER	ns	–
I3CC_SDA Data Setup Time During Open-Drain Mode	t_{SU_OD}	(I3C_OD_LCNT – SDA_TX_HOLD)*GCLK_PER	ns	–
Clock After START Condition	t_CAS	I3C_HC_FREE*GCLK_PER	ns	–
Clock Before STOP Condition	t_CBP	I3C_HC_FREE*GCLK_PER	ns	–

Note:

GCLK_PER is the period of the I3CC clock.

Table 9-79. I3C Push-Pull Timing Parameters for SDR and HDR-DDR Modes⁽¹⁾
Parameter	Symbol	I3C Push-Pull Mode	Units	Notes
SCL Clock Frequency	f_SCL	1/((I3C_PP_LCNT+ I3C_PP_ HCNT)*GCLK_PER)	MHz	–
SCL Clock Low Period	t_LOW	I3C_PP_LCNT*GCLK_PER	ns	For HDR-DDR mode, the I3C_PP_HCNT register is considered for Low period. This is because the Legacy I2C devices must not see the transitions of DDR mode and it must be filtered out with spike filters in I2C.
SCL Clock High Period (Mixed and Pure Bus)	t_HIGH	I3C_PP_HCNT*GCLK_PER	ns	–
I3CC_SDA Signal Data Hold in Push-Pull mode	t_{HD_PP}	SDA_TX_HOLD*GCLK_PER	ns	Data hold is considered for the write transfer from the I3CC alone point of view. The system delays are not considered.
I3CC_SDA Signal Data Setup in Push-Pull mode	t_{SU_PP}	(I3C_PP_LCNT- SDA_TX_HOLD)*GCLK_PER	ns	Data setup is considered for the write transfer from the I3CC alone point of view. The system delays are not considered.
Clock After Repeated START	t_CASr	I3C_HC_FREE*GCLK_PER	ns	–
Clock Before Repeated START	t_CBSr	I3C_HC_FREE*GCLK_PER	ns	–

Note:

GCLK_PER is the period of the I3CC clock.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.