9.7 Register Summary


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00	I3CC_HCI_VERSION	31:24	VERSION[31:24]
		23:16	VERSION[23:16]
		15:8	VERSION[15:8]
		7:0	VERSION[7:0]
0x04	I3CC_HC_CONTROL	31:24	BUS_ENABLE	RESUME	ABORT
		23:16
		15:8								HOT_JOIN_CTRL
		7:0	I2C_DEV_PRESENT							IBA_INCLUDE
0x08	I3CC_CONTROLLER_DEVICE_ADDR	31:24	DYNAMIC_ADDR_VALID
		23:16		DYNAMIC_ADDR[6:0]
		15:8
		7:0
0x0C	I3CC_HC_CAPABILITIES	31:24
		23:16
		15:8
		7:0	HDR_TS_EN	HDR_DDR_EN	STANDBY_CR_CAP		AUTO_COMMAND	COMBO_COMMAND
0x10	I3CC_RESET_CONTROL	31:24
		23:16
		15:8
		7:0			IBI_QUEUE_RST	RX_FIFO_RST	TX_FIFO_RST	RESP_QUEUE_RST	CMD_QUEUE_RST	SOFT_RST
0x14	I3CC_PRESENT_STATE	31:24
		23:16
		15:8
		7:0						CURRENT_CONTROLLER
0x18 ... 0x1F	Reserved
0x20	I3CC_INTR_STATUS	31:24
		23:16
		15:8						HC_INTERNAL_ERR_STAT
		7:0
0x24	I3CC_INTR_STATUS_ENABLE	31:24
		23:16
		15:8						HC_INTERNAL_ERR_STAT_EN
		7:0
0x28	I3CC_INTR_SIGNAL_ENABLE	31:24
		23:16
		15:8						HC_INTERNAL_ERR_SIGNAL_EN
		7:0
0x2C	I3CC_INTR_FORCE	31:24
		23:16
		15:8						INTR_FORCE
		7:0
0x30	I3CC_DAT_SECTION_OFFSET	31:24
		23:16							TABLE_SIZE[5:4]
		15:8	TABLE_SIZE[3:0]				TABLE_OFFSET[11:8]
		7:0	TABLE_OFFSET[7:0]
0x34	I3CC_DCT_SECTION_OFFSET	31:24
		23:16			TABLE_INDEX[2:0]			TABLE_SIZE[6:4]
		15:8	TABLE_SIZE[3:0]				TABLE_OFFSET[11:8]
		7:0	TABLE_OFFSET[7:0]
0x38	I3CC_RING_HEADERS_SECTION_OFFSET	31:24
		23:16
		15:8	SECTION_OFFSET[15:8]
		7:0	SECTION_OFFSET[7:0]
0x3C	I3CC_PIO_SECTION_OFFSET	31:24
		23:16
		15:8	SECTION_OFFSET[15:8]
		7:0	SECTION_OFFSET[7:0]
0x40	I3CC_EXT_CAPS_SECTION_OFFSET	31:24
		23:16
		15:8	SECTION_OFFSET[15:8]
		7:0	SECTION_OFFSET[7:0]
0x44 ... 0x57	Reserved
0x58	I3CC_IBI_NOTIFY_CTRL	31:24
		23:16
		15:8
		7:0					NOTIFY_IBI_REJECTED		NOTIFY_CRR_REJECTED	NOTIFY_HJ_REJECTED
0x5C ... 0x5F	Reserved
0x60	I3CC_DEV_CTX_BASE_LO	31:24	BASE_LO[31:24]
		23:16	BASE_LO[23:16]
		15:8	BASE_LO[15:8]
		7:0	BASE_LO[7:0]
0x64	I3CC_DEV_CTX_BASE_HI	31:24	BASE_HI[31:24]
		23:16	BASE_HI[23:16]
		15:8	BASE_HI[15:8]
		7:0	BASE_HI[7:0]
0x68 ... 0xBF	Reserved
0xC0	I3CC_COMMAND_QUEUE_PORT	31:24	COMMAND[31:24]
		23:16	COMMAND[23:16]
		15:8	COMMAND[15:8]
		7:0	COMMAND[7:0]
0xC4	I3CC_RESPONSE_QUEUE_PORT	31:24	ERR_STATUS[3:0]				TID[3:0]
		23:16
		15:8	DATA_LENGTH[15:8]
		7:0	DATA_LENGTH[7:0]
0xC8	I3CC_XFER_DATA_PORT	31:24	DATA[31:24]
		23:16	DATA[23:16]
		15:8	DATA[15:8]
		7:0	DATA[7:0]
0xCC	I3CC_IBI_PORT	31:24	IBI_DATA[31:24]
		23:16	IBI_DATA[23:16]
		15:8	IBI_DATA[15:8]
		7:0	IBI_DATA[7:0]
0xD0	I3CC_QUEUE_THLD_CTRL	31:24	IBI_STATUS_THLD[7:0]
		23:16	IBI_DATA_SEGMENT_SIZE[7:0]
		15:8	RESP_BUF_THLD[7:0]
		7:0	CMD_EMPTY_BUF_THLD[7:0]
0xD4	I3CC_DATA_BUFFER_THLD_CTRL	31:24						RX_START_THLD[2:0]
		23:16						TX_START_THLD[2:0]
		15:8						RX_BUF_THLD[2:0]
		7:0						TX_BUF_THLD[2:0]
0xD8	I3CC_QUEUE_SIZE	31:24	TX_DATA_BUFFER_SIZE[7:0]
		23:16	RX_DATA_BUFFER_SIZE[7:0]
		15:8	IBI_STATUS_SIZE[7:0]
		7:0	CR_QUEUE_SIZE[7:0]
0xDC ... 0xDF	Reserved
0xE0	I3CC_PIO_INTR_STATUS	31:24
		23:16
		15:8							TRANSFER_ERR_STAT
		7:0			TRANSFER_ABORT_STAT	RESP_READY_STAT	CMD_QUEUE_READY_STAT	IBI_STATUS_THLD_STAT	RX_THLD_STAT	TX_THLD_STAT
0xE4	I3CC_PIO_INTR_STATUS_ENABLE	31:24
		23:16
		15:8							TRANSFER_ERR_STAT_EN
		7:0			TRANSFER_ABORT_STAT_EN	RESP_READY_STAT_EN	CMD_QUEUE_READY_STAT_EN	IBI_STATUS_THLD_STAT_EN	RX_THLD_STAT_EN	TX_THLD_STAT_EN
0xE8	I3CC_PIO_INTR_SIGNAL_ENABLE	31:24
		23:16
		15:8							TRANSFER_ERR_SIGNAL_EN
		7:0			TRANSFER_ABORT_SIGNAL_EN	RESP_READY_SIGNAL_EN	CMD_QUEUE_READY_SIGNAL_EN	IBI_STATUS_THLD_SIGNAL_EN	RX_THLD_SIGNAL_EN	TX_THLD_SIGNAL_EN
0xEC	I3CC_PIO_INTR_FORCE	31:24
		23:16
		15:8							TRANSFER_ERR_FORCE
		7:0			TRANSFER_ABORT_FORCE	RESP_READY_FORCE	CMD_QUEUE_READY_FORCE	IBI_STATUS_THLD_FORCE	RX_THLD_FORCE	TX_THLD_FORCE
0xF0 ... 0x01FF	Reserved
0x0200	I3CC_HW_IDENTIFICATION_HEADER	31:24
		23:16	CAP_LEN[15:8]
		15:8	CAP_LEN[7:0]
		7:0	CAP_ID[7:0]
0x0204	I3CC_COMP_MANUFACTURER	31:24	MIPI_VENDOR_ID[31:24]
		23:16	MIPI_VENDOR_ID[23:16]
		15:8	MIPI_VENDOR_ID[15:8]
		7:0	MIPI_VENDOR_ID[7:0]
0x0208	I3CC_COMP_VERSION	31:24	I3C_VER_ID[31:24]
		23:16	I3C_VER_ID[23:16]
		15:8	I3C_VER_ID[15:8]
		7:0	I3C_VER_ID[7:0]
0x020C	I3CC_COMP_TYPE	31:24	I3C_PRODUCT_ID[31:24]
		23:16	I3C_PRODUCT_ID[23:16]
		15:8	I3C_PRODUCT_ID[15:8]
		7:0	I3C_PRODUCT_ID[7:0]
0x0210	I3CC_BUS_TIMING_HEADER	31:24
		23:16	CAP_LEN[15:8]
		15:8	CAP_LEN[7:0]
		7:0	CAP_ID[7:0]
0x0214	I3CC_SCL_I3C_OD_TIMING	31:24
		23:16	I3C_OD_HCNT[7:0]
		15:8
		7:0	I3C_OD_LCNT[7:0]
0x0218	I3CC_SCL_I3C_PP_TIMING	31:24
		23:16	I3C_PP_HCNT[7:0]
		15:8
		7:0	I3C_PP_LCNT[7:0]
0x021C	I3CC_SCL_I2C_FM_TIMING	31:24
		23:16	I2C_FM_HCNT[7:0]
		15:8
		7:0	I2C_FM_LCNT[7:0]
0x0220	I3CC_SCL_I2C_FMP_TIMING	31:24
		23:16	I2C_FMP_HCNT[7:0]
		15:8
		7:0	I2C_FMP_LCNT[7:0]
0x0224	I3CC_SCL_I2C_SS_TIMING	31:24
		23:16	I2C_SS_HCNT[7:0]
		15:8
		7:0	I2C_SS_LCNT[7:0]
0x0228	I3CC_SCL_EXT_LCNT_TIMING	31:24	I3C_EXT_LCNT_4[7:0]
		23:16	I3C_EXT_LCNT_3[7:0]
		15:8	I3C_EXT_LCNT_2[7:0]
		7:0	I3C_EXT_LCNT_1[7:0]
0x022C	I3CC_SCL_EXT_TERMN_LCNT_TIMING	31:24
		23:16
		15:8
		7:0					I3C_EXT_TERMN_LCNT[3:0]
0x0230	I3CC_SDA_HOLD_SWITCH_DLY_TIMING	31:24
		23:16						SDA_TX_HOLD[2:0]
		15:8						SDA_PP_OD_SWITCH_DLY[2:0]
		7:0						SDA_OD_PP_SWITCH_DLY[2:0]
0x0234	I3CC_BUS_FREE_TIMING	31:24
		23:16
		15:8	I3C_HC_FREE[15:8]
		7:0	I3C_HC_FREE[7:0]
0x0238 ... 0x023B	Reserved
0x023C	I3CC_SCL_LOW_MST_EXT_TIMEOUT	31:24							SCL_LOW_MST_TIMEOUT_COUNT[25:24]
		23:16	SCL_LOW_MST_TIMEOUT_COUNT[23:16]
		15:8	SCL_LOW_MST_TIMEOUT_COUNT[15:8]
		7:0	SCL_LOW_MST_TIMEOUT_COUNT[7:0]
0x0240	I3CC_DS_EXTCAP_HEADER	31:24
		23:16	CAP_LEN[15:8]
		15:8	CAP_LEN[7:0]
		7:0	CAP_ID[7:0]
0x0244	I3CC_QUEUE_STATUS_LEVEL	31:24	IBI_STATUS_CNT[7:0]
		23:16	IBI_BUFFER_LVL[7:0]
		15:8	RESPONSE_BUFFER_LVL[7:0]
		7:0	CMD_QUEUE_FREE_LVL[7:0]
0x0248	I3CC_DATA_BUFFER_STATUS_LEVEL	31:24
		23:16
		15:8	RX_BUF_LVL[7:0]
		7:0	TX_BUF_FREE_LVL[7:0]
0x024C	I3CC_PRESENT_STATE_DEBUG	31:24				HC_IDLE	CMD_TID[3:0]
		23:16			CM_TFR_ST_STATUS[5:0]
		15:8			CM_TFR_STATUS[5:0]
		7:0							SDA_LINE_SIGNAL_LEVEL	SCL_LINE_SIGNAL_LEVEL
0x0250 ... 0x0253	Reserved
0x0254	I3CC_CONTROLLER_EXT_HEADER	31:24
		23:16	CAP_LEN[15:8]
		15:8	CAP_LEN[7:0]
		7:0	CAP_ID[7:0]
0x0258	I3CC_CONTROLLER_CONFIG	31:24
		23:16
		15:8
		7:0			OPERATION_MODE[1:0]