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32-bit Arm Cortex-M23 Low Power MCU with Security, Safety, CAN-FD, Full Speed USB, Touch and Advanced Analog
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PIC32CM5112GC00048
PIC32CM5112GC00064
PIC32CM5112GC00100
PIC32CM5112SG00048
PIC32CM5112SG00064
PIC32CM5112SG00100
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40
Timer/Counter for Control Applications (TCC)
40.5
Functional Description
40.5.2
Basic Operation
40.5.2.6
Compare Operations
40.5.2.6.4
Normal Pulse-Width Modulation (NPWM)
32-bit Arm® Cortex®-M23 MCU with Security, Functional Safety (FuSa), CAN-FD, Full-Speed USB, Enhanced Touch, and Advanced Analog
1
Guidelines for Getting Started
2
Configuration Summary
3
Ordering Information
4
Block Diagram
5
Pinout and Packaging
6
Signal Description
7
Power Supplies and Startup Considerations
8
Product Mapping
9
Peripherals
10
Processor and Architecture
11
Memories
12
PIC32CM SG00/GC00
Security Features
13
Implementation Defined Attribution Unit (IDAU)
14
System Bus AHB - APB Bridge (H2PB)
15
Multi-Channel RAM Controller (MCRAMC)
16
Peripheral Access Controller (PAC)
17
Device Service Unit (DSU)
18
Clock Distribution System
19
Oscillator Controller (OSCCTRL)
20
Generic Clock Controller (GCLK)
21
Main Clock (MCLK)
22
32 KHz Oscillators Controller (OSC32KCTRL)
23
Watchdog Timer (WDT)
24
Frequency Meter (FREQM)
25
Real-Time Counter (RTC)
26
Direct Memory Access Controller (DMAC)
27
Supply Controller (SUPC)
28
Power Manager (PM)
29
Reset Controller (RSTC)
30
External Interrupt Controller (EIC)
31
Non-Volatile Memory Controller (NVMCTRL)
32
Event System (EVSYS)
33
I/O Pin Controller (PORT)
34
Serial Communication Interface (SERCOM)
35
Controller Area Network (CAN)
36
Universal Serial Bus (USB)
37
Configurable Custom Logic (CCL)
38
Analog to Digital Converter (ADC)
39
Analog Comparator (AC)
40
Timer/Counter for Control Applications (TCC)
40.1
Overview
40.2
Features
40.3
Block Diagram
40.4
Signal Description
40.5
Functional Description
40.5.1
Principle of Operation
40.5.2
Basic Operation
40.5.2.1
Synchronization
40.5.2.2
Initialization
40.5.2.3
Enabling, Disabling, and Resetting
40.5.2.4
Prescaler Selection
40.5.2.5
Counter Operation
40.5.2.6
Compare Operations
40.5.2.6.1
Waveform Output Generation Operations
40.5.2.6.2
Normal Frequency (NFRQ)
40.5.2.6.3
Match Frequency (MFRQ)
40.5.2.6.4
Normal Pulse-Width Modulation (NPWM)
40.5.2.6.5
Normal Pulse-Width Modulation (NPWM) Single-Slope Operation
40.5.2.6.6
Normal Pulse-Width Modulation (NPWM) Dual-Slope Operation
40.5.2.6.7
Dual-Slope Critical PWM Generation
40.5.2.6.8
Dual-Compare PWM Generation
40.5.2.6.9
Output Polarity
40.5.2.7
Double Buffering
40.5.2.8
Capture Operations
40.5.3
Additional Features
40.5.4
DMA, Interrupts, and Events
40.5.5
Sleep Mode Operation
40.6
Peripheral Dependencies
40.7
Register Summary
41
TrustRAM (TRAM)
42
Peripheral Touch Controller (PTC)
43
Hardware Security Module Lite (HSM-Lite)
44
Anti-Tamper Module (AT)
45
Physically Uncloneable Function (PUF)
46
Electrical Characteristics
47
Packaging Information
48
Schematic Checklist
49
Common Conventions
50
Acronyms and Abbreviations
51
Revision History
Microchip Information
40.5.2.6.4 Normal Pulse-Width Modulation (NPWM)
NPWM uses single-slope PWM generation.