32.7 Peripheral Dependencies
| Peripheral Name | Base Address |
NVIC IRQ Index:Source |
MCLK AHB/APB Clock Enable Bus:Register:Bit |
GCLK Peripheral Channel Control Register |
PAC Peripheral Identifier PERID:Register:Bit |
DMA Trigger Index:Source |
Event System Type:Event: Register:Path | Power Domain |
|---|---|---|---|---|---|---|---|---|
| EVSYS | 0x44806000 |
48 : EVD0/OVR0 49 : EVD1/OVR1 50 : EVD2/OVR2 51 : EVD3/OVR3 52 : EVD4/OVR4 53 : EVD5/OVR5 54 : EVD6/OVR6 55 : EVD7/OVR7 56 : EVD8/OVR8 57 : EVD9/OVR9 58 : EVD10/OVR10 59 : EVD11/OVR11 |
APB: CLKMSK[1] MASK3 |
CH0: PCHCTRL[8] CH1: PCHCTRL[9] CH2: PCHCTRL[10] CH3: PCHCTRL[11] CH4: PCHCTRL[12] CH5: PCHCTRL[13] CH6: PCHCTRL[14] CH7: PCHCTRL[15] CH8: PCHCTRL[16] CH9: PCHCTRL[17] CH10: PCHCTRL[18] CH11: PCHCTRL[19] |
25 STATUS0 PERID25 |
PD_CORE_SW |