35.2 Tx Event FIFO Element 1

Table 35-102. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	E1
Offset:	0x004
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	MM[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ET[1:0]		FDF	BRS	DLC[3:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TXTS[15:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TXTS[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bits 31:24 – MM[7:0] Message Marker

Bits 23:22 – ET[1:0] Event Type

Value	Name	Description
1	TXE	Tx event
2	TXC	Transmission in spite of cancellation

Bit 21 – FDF FD Format

Bit 20 – BRS Bit Rate Search

Bits 19:16 – DLC[3:0] Data Length Code

Bits 15:0 – TXTS[15:0] Tx Timestamp

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