26.5 Peripheral Dependencies
| Peripheral Name | Base Address |
NVIC IRQ Index:Source |
MCLK AHB/APB Clock Enable Bus:Register:Bit |
GCLK Peripheral Channel Control Register |
PAC Peripheral Identifier PERID:Register:Bit |
DMA Trigger Index:Source |
Event System Type:Event: Register:Path | Power Domain |
|---|---|---|---|---|---|---|---|---|
| DMAC | 0x44802000 |
42 : TCMPL0/SUSP0/TERR0 43 : TCMPL1/SUSP1/TERR1 44 : TCMPL2/SUSP2/TERR2 45 : TCMPL3/SUSP3/TERR3 46 : TCMPL4/SUSP4/TERR4/TCMPL5/SUSP5/TERR5/TCMPL6/SUSP6/TERR6/TCMPL7/SUSP7/TERR7 |
AHB: CLKMSK[0] MASK28 APB: CLKMSK[0] MASK29 | --- |
21 STATUS0 PERID21 |
Generators: CH0: CHANNEL[37] CH1: CHANNEL[38] CH2: CHANNEL[39] CH3: CHANNEL[40] Users: CH0: USER[6],Resynch CH1: USER[7],Resynch CH2: USER[8],Resynch CH3: USER[9],Resynch |
PD_CORE_SW |