23.6.2 Configuration
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CONFIG |
| Offset: | 0x1 |
| Reset: | 0xBB |
| Property: | RW |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WINDOW[3:0] | PER[3:0] | ||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | |
Bits 7:4 – WINDOW[3:0] Window Mode Time-Out Period
In Window mode, these bits determine the watchdog closed window period as a number of cycles of the 1024 Hz CLK_WDT_OSC clock. These bits are loaded from User Configuration FUCFG0 at start-up.
| Value | Name | Description |
|---|---|---|
| 0x0 | CYC8 | 8 clock cycles |
| 0x1 | CYC16 | 16 clock cycles |
| 0x2 | CYC32 | 32 clock cycles |
| 0x3 | CYC64 | 64 clock cycles |
| 0x4 | CYC128 | 128 clock cycles |
| 0x5 | CYC256 | 256 clock cycles |
| 0x6 | CYC512 | 512 clock cycles |
| 0x7 | CYC1024 | 1024 clock cycles |
| 0x8 | CYC2048 | 2048 clock cycles |
| 0x9 | CYC4096 | 4096 clock cycles |
| 0xA | CYC8192 | 8192 clock cycles |
| 0xB | CYC16384 | 16384 clock cycles |
Bits 3:0 – PER[3:0] Time-Out Period
These bits determine the watchdog time-out period as a number of 1024 Hz CLK_WDTOSC clock cycles. In Window mode operation, these bits define the open window period. These bits are loaded from User Configuration FUCFG0 at startup.
| Value | Name | Description |
|---|---|---|
| 0x0 | CYC8 | 8 clock cycles |
| 0x1 | CYC16 | 16 clock cycles |
| 0x2 | CYC32 | 32 clock cycles |
| 0x3 | CYC64 | 64 clock cycles |
| 0x4 | CYC128 | 128 clock cycles |
| 0x5 | CYC256 | 256 clock cycles |
| 0x6 | CYC512 | 512 clock cycles |
| 0x7 | CYC1024 | 1024 clock cycles |
| 0x8 | CYC2048 | 2048 clock cycles |
| 0x9 | CYC4096 | 4096 clock cycles |
| 0xA | CYC8192 | 8192 clock cycles |
| 0xB | CYC16384 | 16384 clock cycles |